111 lines
4.1 KiB
XML
111 lines
4.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element clk_0
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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element rs232_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="EP4CE6E22C8" />
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<parameter name="deviceFamily" value="Cyclone IV E" />
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<parameter name="deviceSpeedGrade" value="8" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="avalon_rs232_slave" internal="rs232_0.avalon_rs232_slave" />
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<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
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<interface name="interrupt" internal="rs232_0.interrupt" />
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<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
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<interface
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name="rs232_0_avalon_data_receive_source"
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internal="rs232_0.avalon_data_receive_source"
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type="avalon_streaming"
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dir="start">
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<port name="rs232_0_from_uart_ready" internal="from_uart_ready" />
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<port name="rs232_0_from_uart_data" internal="from_uart_data" />
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<port name="rs232_0_from_uart_error" internal="from_uart_error" />
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<port name="rs232_0_from_uart_valid" internal="from_uart_valid" />
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</interface>
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<interface
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name="rs232_0_avalon_data_transmit_sink"
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internal="rs232_0.avalon_data_transmit_sink"
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type="avalon_streaming"
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dir="end">
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<port name="rs232_0_to_uart_data" internal="to_uart_data" />
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<port name="rs232_0_to_uart_error" internal="to_uart_error" />
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<port name="rs232_0_to_uart_valid" internal="to_uart_valid" />
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<port name="rs232_0_to_uart_ready" internal="to_uart_ready" />
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</interface>
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<interface
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name="rs232_0_external_interface"
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internal="rs232_0.external_interface"
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type="conduit"
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dir="end">
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<port name="rs232_0_UART_RXD" internal="UART_RXD" />
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<port name="rs232_0_UART_TXD" internal="UART_TXD" />
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</interface>
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<module name="clk_0" kind="clock_source" version="21.1" enabled="1">
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<parameter name="clockFrequency" value="50000000" />
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<parameter name="clockFrequencyKnown" value="true" />
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<parameter name="inputClockFrequency" value="0" />
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<parameter name="resetSynchronousEdges" value="NONE" />
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</module>
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<module
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name="rs232_0"
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kind="altera_up_avalon_rs232"
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version="17.1"
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enabled="1"
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autoexport="1">
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<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="avalon_bus_type" value="Streaming" />
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<parameter name="baud" value="115200" />
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<parameter name="data_bits" value="8" />
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<parameter name="parity" value="None" />
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<parameter name="stop_bits" value="1" />
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</module>
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<connection kind="clock" version="21.1" start="clk_0.clk" end="rs232_0.clk" />
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<connection
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kind="reset"
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version="21.1"
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start="clk_0.clk_reset"
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end="rs232_0.reset" />
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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