38 lines
2.3 KiB
Verilog
38 lines
2.3 KiB
Verilog
// UART.v
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// Generated using ACDS version 21.1 842
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`timescale 1 ps / 1 ps
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module UART (
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input wire clk_clk, // clk.clk
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input wire reset_reset_n, // reset.reset_n
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input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready
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output wire [7:0] rs232_0_from_uart_data, // .data
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output wire rs232_0_from_uart_error, // .error
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output wire rs232_0_from_uart_valid, // .valid
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input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data
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input wire rs232_0_to_uart_error, // .error
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input wire rs232_0_to_uart_valid, // .valid
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output wire rs232_0_to_uart_ready, // .ready
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input wire rs232_0_clk, // rs232_0_clk.clk
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input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD
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output wire rs232_0_UART_TXD, // .TXD
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input wire rs232_0_reset // rs232_0_reset.reset
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);
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UART_rs232_0 rs232_0 (
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.clk (rs232_0_clk), // clk.clk
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.reset (rs232_0_reset), // reset.reset
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.from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready
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.from_uart_data (rs232_0_from_uart_data), // .data
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.from_uart_error (rs232_0_from_uart_error), // .error
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.from_uart_valid (rs232_0_from_uart_valid), // .valid
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.to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data
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.to_uart_error (rs232_0_to_uart_error), // .error
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.to_uart_valid (rs232_0_to_uart_valid), // .valid
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.to_uart_ready (rs232_0_to_uart_ready), // .ready
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.UART_RXD (rs232_0_UART_RXD), // external_interface.export
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.UART_TXD (rs232_0_UART_TXD) // .export
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);
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endmodule
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