1139 lines
16 KiB
Plaintext
1139 lines
16 KiB
Plaintext
/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_3 -c jyh_4490_3 --vector_source="/home/ir/Documents/codelib/Quartus/v3/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_3 -c jyh_4490_3 --vector_source="/home/ir/Documents/codelib/Quartus/v3/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/" jyh_4490_3 -c jyh_4490_3</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/" jyh_4490_3 -c jyh_4490_3</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_3.vo
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vlog -work work Waveform.vwf.vt
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vsim -voptargs=+acc -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_entry_vlg_vec_tst
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vcd file -direction jyh_4490_3.msim.vcd
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vcd add -internal jyh_4490_3_entry_vlg_vec_tst/*
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vcd add -internal jyh_4490_3_entry_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_3.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_entry_vlg_vec_tst
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vcd file -direction jyh_4490_3.msim.vcd
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vcd add -internal jyh_4490_3_entry_vlg_vec_tst/*
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vcd add -internal jyh_4490_3_entry_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("clk")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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|
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SIGNAL("clr")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("en")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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|
SIGNAL("in0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 4;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("in0[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in0";
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}
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SIGNAL("in0[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in0";
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}
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SIGNAL("in0[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in0";
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}
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SIGNAL("in0[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in0";
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}
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|
SIGNAL("in1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 4;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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|
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SIGNAL("in1[3]")
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|
{
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VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in1";
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}
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SIGNAL("in1[2]")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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|
PARENT = "in1";
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}
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|
SIGNAL("in1[1]")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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|
LSB_INDEX = -1;
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|
DIRECTION = INPUT;
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|
PARENT = "in1";
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|
}
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|
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|
SIGNAL("in1[0]")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
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|
LSB_INDEX = -1;
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|
DIRECTION = INPUT;
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|
PARENT = "in1";
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|
}
|
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SIGNAL("load")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
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|
DIRECTION = INPUT;
|
|
PARENT = "";
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|
}
|
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|
|
SIGNAL("out0")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 4;
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|
LSB_INDEX = 0;
|
|
DIRECTION = OUTPUT;
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|
PARENT = "";
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|
}
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|
|
SIGNAL("out0[3]")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
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|
PARENT = "out0";
|
|
}
|
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|
|
SIGNAL("out0[2]")
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|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "out0";
|
|
}
|
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|
SIGNAL("out0[1]")
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|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
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|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
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|
DIRECTION = OUTPUT;
|
|
PARENT = "out0";
|
|
}
|
|
|
|
SIGNAL("out0[0]")
|
|
{
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|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "out0";
|
|
}
|
|
|
|
SIGNAL("out1")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 4;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("out1[3]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "out1";
|
|
}
|
|
|
|
SIGNAL("out1[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "out1";
|
|
}
|
|
|
|
SIGNAL("out1[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "out1";
|
|
}
|
|
|
|
SIGNAL("out1[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "out1";
|
|
}
|
|
|
|
SIGNAL("upd")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("CO")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("clk2")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = INPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("code")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 7;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("code[6]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("code[5]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("code[4]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("code[3]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("code[2]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("code[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("code[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "code";
|
|
}
|
|
|
|
SIGNAL("sel")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = BUS;
|
|
WIDTH = 2;
|
|
LSB_INDEX = 0;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "";
|
|
}
|
|
|
|
SIGNAL("sel[1]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "sel";
|
|
}
|
|
|
|
SIGNAL("sel[0]")
|
|
{
|
|
VALUE_TYPE = NINE_LEVEL_BIT;
|
|
SIGNAL_TYPE = SINGLE_BIT;
|
|
WIDTH = 1;
|
|
LSB_INDEX = -1;
|
|
DIRECTION = OUTPUT;
|
|
PARENT = "sel";
|
|
}
|
|
|
|
TRANSITION_LIST("clk")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 50;
|
|
LEVEL 0 FOR 10.0;
|
|
LEVEL 1 FOR 10.0;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("clr")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("en")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in0[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in0[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in0[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in0[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in1[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in1[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 1 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in1[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("in1[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("load")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out0[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out0[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out0[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out0[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out1[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out1[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out1[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("out1[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("upd")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL 0 FOR 500.0;
|
|
LEVEL 1 FOR 500.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("CO")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("clk2")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
NODE
|
|
{
|
|
REPEAT = 200;
|
|
LEVEL 0 FOR 2.5;
|
|
LEVEL 1 FOR 2.5;
|
|
}
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[6]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[5]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[4]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[3]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[2]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("code[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("sel[1]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
TRANSITION_LIST("sel[0]")
|
|
{
|
|
NODE
|
|
{
|
|
REPEAT = 1;
|
|
LEVEL X FOR 1000.0;
|
|
}
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "clk";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 0;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "clk2";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 1;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "clr";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 2;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "upd";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 3;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "en";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 4;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in0";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 5;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 6, 7, 8, 9;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in0[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 6;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 5;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in0[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 7;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 5;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in0[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 8;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 5;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in0[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 9;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 5;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in1";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 10;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 11, 12, 13, 14;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in1[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 11;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 10;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in1[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 12;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 10;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in1[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 13;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 10;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "in1[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 14;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 10;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "load";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 15;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "CO";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 16;
|
|
TREE_LEVEL = 0;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out0";
|
|
EXPAND_STATUS = EXPANDED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 17;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 18, 19, 20, 21;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out0[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 18;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 17;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out0[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 19;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 17;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out0[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 20;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 17;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out0[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 21;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 17;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out1";
|
|
EXPAND_STATUS = EXPANDED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 22;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 23, 24, 25, 26;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out1[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 23;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 22;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out1[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 24;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 22;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out1[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 25;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 22;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "out1[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Unsigned;
|
|
TREE_INDEX = 26;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 22;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 27;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 28, 29, 30, 31, 32, 33, 34;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[6]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 28;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[5]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 29;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[4]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 30;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[3]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 31;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[2]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 32;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 33;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "code[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 34;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 27;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "sel";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 35;
|
|
TREE_LEVEL = 0;
|
|
CHILDREN = 36, 37;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "sel[1]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 36;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 35;
|
|
}
|
|
|
|
DISPLAY_LINE
|
|
{
|
|
CHANNEL = "sel[0]";
|
|
EXPAND_STATUS = COLLAPSED;
|
|
RADIX = Binary;
|
|
TREE_INDEX = 37;
|
|
TREE_LEVEL = 1;
|
|
PARENT = 35;
|
|
}
|
|
|
|
TIME_BAR
|
|
{
|
|
TIME = 0;
|
|
MASTER = TRUE;
|
|
}
|
|
;
|