22 lines
359 B
Verilog
22 lines
359 B
Verilog
//译码器模块
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module jyh_4490_2_2(out,in);
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input[2:0] in;
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output[6:0] out;
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reg[7:0] out;
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always @ (in)
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begin
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case (in)
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3'd0: out<=7'b0000001;
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3'd1: out<=7'b0000011;
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3'd2: out<=7'b0000111;
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3'd3: out<=7'b0001111;
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3'd4: out<=7'b0011111;
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3'd5: out<=7'b0111111;
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3'd6: out<=7'b0000000;
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default: out=7'bx;
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endcase
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end
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endmodule
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