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justhomework/Quartus/Design/UART/synthesis/submodules
2022-05-28 00:35:55 +08:00
..
altera_up_rs232_counters.v 暂且不知道这堆东西能不能用 2022-05-28 00:35:55 +08:00
altera_up_rs232_in_deserializer.v 暂且不知道这堆东西能不能用 2022-05-28 00:35:55 +08:00
altera_up_rs232_out_serializer.v 暂且不知道这堆东西能不能用 2022-05-28 00:35:55 +08:00
altera_up_sync_fifo.v 暂且不知道这堆东西能不能用 2022-05-28 00:35:55 +08:00
UART_rs232_0.v 暂且不知道这堆东西能不能用 2022-05-28 00:35:55 +08:00