This repository has been archived on 2024-01-06. You can view files and clone it, but cannot push or open issues or pull requests.
justhomework/Quartus/v3/jyh_4490_3_encoder.v
2022-04-05 16:19:24 +08:00

57 lines
No EOL
1.1 KiB
Verilog

module jyh_4490_3_encoder(codeout,indec,indec2,clk,seg);
input[3:0] indec,indec2;
input clk;
output reg [1:0] seg=2'b01;
output reg [6:0] codeout;
reg n = 1;
always @ (posedge clk)
begin
if(n==1)
begin
n<=2;
if(seg==2'b01)
begin
case (indec)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
if(seg==2'b10)
begin
case (indec2)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
end
if(n==2)
begin
n<=1;
codeout<=7'b0;
if(seg==2'b10)
seg<=2'b01;
else if(seg==2'b10)
seg<=2'b01;
end
end
endmodule