57 lines
No EOL
1.1 KiB
Verilog
57 lines
No EOL
1.1 KiB
Verilog
module jyh_4490_3_encoder(codeout,indec,indec2,clk,seg);
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input[3:0] indec,indec2;
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input clk;
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output reg [1:0] seg=2'b01;
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output reg [6:0] codeout;
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reg n = 1;
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always @ (posedge clk)
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begin
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if(n==1)
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begin
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n<=2;
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if(seg==2'b01)
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begin
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case (indec)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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if(seg==2'b10)
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begin
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case (indec2)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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end
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if(n==2)
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begin
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n<=1;
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codeout<=7'b0;
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if(seg==2'b10)
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seg<=2'b01;
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else if(seg==2'b10)
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seg<=2'b01;
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end
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end
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endmodule |