187 lines
5.9 KiB
Verilog
187 lines
5.9 KiB
Verilog
// (C) 2001-2021 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
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// IN THIS FILE.
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/******************************************************************************
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* *
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* This module reads and writes data to the RS232 connector on Altera's *
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* DE-series Development and Education Boards. *
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* *
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******************************************************************************/
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module UART_rs232_0 (
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// Inputs
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clk,
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reset,
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from_uart_ready,
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to_uart_data,
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to_uart_error,
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to_uart_valid,
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UART_RXD,
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// Bidirectionals
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// Outputs
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from_uart_data,
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from_uart_error,
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from_uart_valid,
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to_uart_ready,
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UART_TXD
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);
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/*****************************************************************************
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* Parameter Declarations *
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*****************************************************************************/
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parameter CW = 0; // Baud counter width
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parameter BAUD_TICK_COUNT = 0;
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parameter HALF_BAUD_TICK_COUNT = 0;
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parameter TDW = 10; // Total data width
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parameter DW = 8; // Data width
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parameter ODD_PARITY = 1'b0;
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/*****************************************************************************
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* Port Declarations *
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*****************************************************************************/
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// Inputs
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input clk;
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input reset;
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input from_uart_ready;
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input [(DW-1):0] to_uart_data;
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input to_uart_error;
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input to_uart_valid;
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input UART_RXD;
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// Bidirectionals
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// Outputs
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output [(DW-1):0] from_uart_data;
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output from_uart_error;
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output from_uart_valid;
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output to_uart_ready;
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output UART_TXD;
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/*****************************************************************************
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* Constant Declarations *
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*****************************************************************************/
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/*****************************************************************************
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* Internal Wires and Registers Declarations *
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*****************************************************************************/
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// Internal Wires
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wire [(DW-1):0] read_data;
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wire write_data_parity;
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wire [ 7: 0] write_space;
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// Internal Registers
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// State Machine Registers
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/*****************************************************************************
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* Finite State Machine(s) *
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*****************************************************************************/
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/*****************************************************************************
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* Sequential Logic *
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*****************************************************************************/
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// Output Registers
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// Internal Registers
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/*****************************************************************************
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* Combinational Logic *
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*****************************************************************************/
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// Output Assignments
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assign from_uart_data = read_data;
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assign from_uart_error = 1'b0;
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assign to_uart_ready = (|(write_space));
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// Internal Assignments
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assign write_data_parity = (^(to_uart_data)) ^ ODD_PARITY;
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/*****************************************************************************
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* Internal Modules *
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*****************************************************************************/
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altera_up_rs232_in_deserializer RS232_In_Deserializer (
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// Inputs
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.clk (clk),
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.reset (reset),
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.serial_data_in (UART_RXD),
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.receive_data_en (from_uart_ready),
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// Bidirectionals
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// Outputs
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.fifo_read_available (),
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.received_data_valid (from_uart_valid),
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.received_data (read_data)
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);
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defparam
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RS232_In_Deserializer.CW = CW,
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RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
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RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
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RS232_In_Deserializer.TDW = TDW,
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RS232_In_Deserializer.DW = (DW - 1);
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altera_up_rs232_out_serializer RS232_Out_Serializer (
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// Inputs
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.clk (clk),
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.reset (reset),
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.transmit_data (to_uart_data),
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.transmit_data_en (to_uart_valid & to_uart_ready),
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// Bidirectionals
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// Outputs
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.fifo_write_space (write_space),
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.serial_data_out (UART_TXD)
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);
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defparam
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RS232_Out_Serializer.CW = CW,
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RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
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RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
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RS232_Out_Serializer.TDW = TDW,
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RS232_Out_Serializer.DW = (DW - 1);
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endmodule
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