50 lines
No EOL
723 B
Verilog
50 lines
No EOL
723 B
Verilog
`timescale 1ns/1ns
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module jyh_4490_6_testbench_top;
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reg clk;
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wire [6:0] code;
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wire [7:0] seg;
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wire [19:0] cnt;
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reg clr;
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reg in;
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reg en;
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wire subclk;
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wire [3:0] out0;
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wire [3:0] out1;
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initial begin
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clk=0;
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in=0;
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clr=1;
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en=1;
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end
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always#10 clk=~clk;
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always
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begin
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in=0;
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#15000000;
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repeat(5)
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begin
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in=1;
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#1000000;
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in=0;
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#1000000;
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end
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in=1;
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#30000000;
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repeat(5)
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begin
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in=0;
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#1000000;
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in=1;
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#1000000;
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end
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in=0;
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#15000000;
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end
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jyh_4490_6_entry E1(.code(code),.seg(seg),.clk_50m(clk),.clr(clr),.en(en),.in(in),
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//数码管型码 数码管位码 50M 清零信号 使能信号 按键
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.out0(out0),.out1(out1),.subclk(subclk));
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//计数值 消抖值
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endmodule |