57 lines
652 B
Verilog
57 lines
652 B
Verilog
module jyh_4490_3_counter(Q,clk,clr,load,in,en,upd,co);
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input[3:0] in;
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input en,clk,clr,load,upd;
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output reg [3:0] Q;
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output reg co;
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always@(posedge clk,negedge clr)
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begin
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//异步清零
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if(!clr)
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Q<=0;
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else if(en)
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begin
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//同步置数
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if(load)
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begin
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Q<=in;
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co<=1'b1;
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end
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//正反计数
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else if(upd)
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begin
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if(Q>=4'd9)
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begin
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Q<=4'd0;
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co<=1'b1;
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end
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else
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begin
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Q <= Q+1;
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co<=0;
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end
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end
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else
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begin
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if(Q<=4'd0)
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begin
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Q<=4'd9;
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co<=1'b1;
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end
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else
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begin
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Q <= Q-1;
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co<=0;
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end
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end
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end
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else
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Q<=0;
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end
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endmodule
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