279 lines
6 KiB
Text
279 lines
6 KiB
Text
/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_7.vo
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vlog -work work Waveform.vwf.vt
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vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
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vcd file -direction jyh_4490_7.msim.vcd
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_7.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
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vcd file -direction jyh_4490_7.msim.vcd
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("clk")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("f0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("f1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("f2")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("p")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("sta")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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TRANSITION_LIST("clk")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 1000;
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LEVEL 0 FOR 0.5;
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LEVEL 1 FOR 0.5;
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}
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}
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}
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TRANSITION_LIST("f0")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 20.0;
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LEVEL 1 FOR 40.0;
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LEVEL 0 FOR 40.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 60.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 40.0;
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LEVEL 1 FOR 10.0;
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LEVEL 0 FOR 100.0;
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LEVEL 1 FOR 60.0;
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LEVEL 0 FOR 30.0;
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LEVEL 1 FOR 50.0;
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LEVEL 0 FOR 50.0;
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LEVEL 1 FOR 30.0;
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LEVEL 0 FOR 50.0;
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LEVEL 1 FOR 30.0;
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LEVEL 0 FOR 50.0;
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LEVEL 1 FOR 10.0;
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LEVEL 0 FOR 90.0;
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LEVEL 1 FOR 30.0;
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LEVEL 0 FOR 170.0;
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}
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}
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TRANSITION_LIST("f1")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("f2")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("p")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 280.0;
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LEVEL 1 FOR 720.0;
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}
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}
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TRANSITION_LIST("sta")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 660.0;
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LEVEL 1 FOR 340.0;
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "clk";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "f0";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "f1";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "f2";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 3;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "p";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 4;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "sta";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 5;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;
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