89 lines
No EOL
1.2 KiB
Verilog
89 lines
No EOL
1.2 KiB
Verilog
module jyh_4490_7_is(f2,f1,f0,clk,p,sta);
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input p,sta,f0,clk;
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output reg f2,f1;
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reg flag,flag2;//counter enable flag
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parameter TARGET=15000; //0.3ms
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parameter TARGET2=5000; //0.1ms
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reg [13:0] count;//2^14=16384
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reg [14:0] count2;//2^15=32768
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reg negf0; //whether f0 enter low level
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initial begin
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flag=0;
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flag2=0;
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count=0;
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negf0=0;
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end
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always@(posedge clk)
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begin
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if(!f0)
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negf0<=1;
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if(f0&&negf0)
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begin
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negf0<=0;
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flag<=1;
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flag2<=1;
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f1<=1;
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f2<=1;
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end
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else
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begin
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//xinchong
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if(count>=TARGET)
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begin
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flag<=0;
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f1<=0;
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end
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//shaochong
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if(p)
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begin
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if(sta)
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begin
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if(count2>=5*TARGET2)
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begin
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f2<=0;
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flag2<=0;
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//end of a circle
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end
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else if(count2>=4*TARGET2)
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f2<=1;
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else if(count2>=3*TARGET2)
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f2<=0;
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else if(count2>=2*TARGET2)
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f2<=1;
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else if(count2>=TARGET2)
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f2<=0;
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end
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else if(count>=3*TARGET2)
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begin
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f2<=0;
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flag2<=0;
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//end of a circle
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end
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else if(count>=2*TARGET2)
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f2<=1;
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else if(count>=TARGET2)
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f2<=0;
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end
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else
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f2<=f1;
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//whether to add counter
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if(flag)
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count<=count+1;
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else
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count<=0;
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if(flag2)
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count2<=count2+1;
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else
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count2<=0;
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end
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end
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endmodule |