36 lines
1.6 KiB
Text
36 lines
1.6 KiB
Text
/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_6_divider
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Top level modules:
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jyh_4490_6_divider
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} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_6_counter
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Top level modules:
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jyh_4490_6_counter
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} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_4_encoder
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Top level modules:
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jyh_4490_4_encoder
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} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_6_testbench
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Top level modules:
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jyh_4490_6_testbench
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} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_mstate
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Top level modules:
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jyh_4490_mstate
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} {} {}}
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