101 lines
5.5 KiB
Verilog
101 lines
5.5 KiB
Verilog
// uart_screen.v
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// Generated using ACDS version 21.1 842
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`timescale 1 ps / 1 ps
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module uart_screen (
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input wire clk_clk, // clk.clk
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input wire reset_reset_n, // reset.reset_n
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input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready
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output wire [7:0] rs232_0_from_uart_data, // .data
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output wire rs232_0_from_uart_error, // .error
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output wire rs232_0_from_uart_valid, // .valid
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input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data
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input wire rs232_0_to_uart_error, // .error
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input wire rs232_0_to_uart_valid, // .valid
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output wire rs232_0_to_uart_ready, // .ready
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input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD
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output wire rs232_0_UART_TXD // .TXD
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);
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> rs232_0:reset
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uart_screen_rs232_0 rs232_0 (
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.clk (clk_clk), // clk.clk
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.reset (rst_controller_reset_out_reset), // reset.reset
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.from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready
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.from_uart_data (rs232_0_from_uart_data), // .data
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.from_uart_error (rs232_0_from_uart_error), // .error
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.from_uart_valid (rs232_0_from_uart_valid), // .valid
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.to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data
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.to_uart_error (rs232_0_to_uart_error), // .error
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.to_uart_valid (rs232_0_to_uart_valid), // .valid
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.to_uart_ready (rs232_0_to_uart_ready), // .ready
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.UART_RXD (rs232_0_UART_RXD), // external_interface.export
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.UART_TXD (rs232_0_UART_TXD) // .export
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);
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altera_reset_controller #(
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.NUM_RESET_INPUTS (1),
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.OUTPUT_RESET_SYNC_EDGES ("deassert"),
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.SYNC_DEPTH (2),
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.RESET_REQUEST_PRESENT (0),
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.RESET_REQ_WAIT_TIME (1),
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.MIN_RST_ASSERTION_TIME (3),
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.RESET_REQ_EARLY_DSRT_TIME (1),
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.USE_RESET_REQUEST_IN0 (0),
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.USE_RESET_REQUEST_IN1 (0),
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.USE_RESET_REQUEST_IN2 (0),
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.USE_RESET_REQUEST_IN3 (0),
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.USE_RESET_REQUEST_IN4 (0),
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.USE_RESET_REQUEST_IN5 (0),
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.USE_RESET_REQUEST_IN6 (0),
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.USE_RESET_REQUEST_IN7 (0),
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.USE_RESET_REQUEST_IN8 (0),
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.USE_RESET_REQUEST_IN9 (0),
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.USE_RESET_REQUEST_IN10 (0),
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.USE_RESET_REQUEST_IN11 (0),
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.USE_RESET_REQUEST_IN12 (0),
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.USE_RESET_REQUEST_IN13 (0),
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.USE_RESET_REQUEST_IN14 (0),
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.USE_RESET_REQUEST_IN15 (0),
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.ADAPT_RESET_REQUEST (0)
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) rst_controller (
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.reset_in0 (~reset_reset_n), // reset_in0.reset
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.clk (clk_clk), // clk.clk
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.reset_out (rst_controller_reset_out_reset), // reset_out.reset
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.reset_req (), // (terminated)
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.reset_req_in0 (1'b0), // (terminated)
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.reset_in1 (1'b0), // (terminated)
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.reset_req_in1 (1'b0), // (terminated)
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.reset_in2 (1'b0), // (terminated)
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.reset_req_in2 (1'b0), // (terminated)
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.reset_in3 (1'b0), // (terminated)
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.reset_req_in3 (1'b0), // (terminated)
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.reset_in4 (1'b0), // (terminated)
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.reset_req_in4 (1'b0), // (terminated)
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.reset_in5 (1'b0), // (terminated)
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.reset_req_in5 (1'b0), // (terminated)
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.reset_in6 (1'b0), // (terminated)
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.reset_req_in6 (1'b0), // (terminated)
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.reset_in7 (1'b0), // (terminated)
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.reset_req_in7 (1'b0), // (terminated)
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.reset_in8 (1'b0), // (terminated)
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.reset_req_in8 (1'b0), // (terminated)
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.reset_in9 (1'b0), // (terminated)
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.reset_req_in9 (1'b0), // (terminated)
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.reset_in10 (1'b0), // (terminated)
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.reset_req_in10 (1'b0), // (terminated)
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.reset_in11 (1'b0), // (terminated)
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.reset_req_in11 (1'b0), // (terminated)
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.reset_in12 (1'b0), // (terminated)
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.reset_req_in12 (1'b0), // (terminated)
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.reset_in13 (1'b0), // (terminated)
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.reset_req_in13 (1'b0), // (terminated)
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.reset_in14 (1'b0), // (terminated)
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.reset_req_in14 (1'b0), // (terminated)
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.reset_in15 (1'b0), // (terminated)
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.reset_req_in15 (1'b0) // (terminated)
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);
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endmodule
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