30 lines
1.6 KiB
Text
30 lines
1.6 KiB
Text
Info: Starting: Create block symbol file (.bsf)
|
|
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8
|
|
Progress: Loading Design/uart_screen.qsys
|
|
Progress: Reading input file
|
|
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
|
|
Progress: Parameterizing module rs232_0
|
|
Progress: Building connections
|
|
Progress: Parameterizing connections
|
|
Progress: Validating
|
|
Progress: Done reading input file
|
|
Info: qsys-generate succeeded.
|
|
Info: Finished: Create block symbol file (.bsf)
|
|
Info:
|
|
Info: Starting: Create HDL design files for synthesis
|
|
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
|
|
Progress: Loading Design/uart_screen.qsys
|
|
Progress: Reading input file
|
|
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
|
|
Progress: Parameterizing module rs232_0
|
|
Progress: Building connections
|
|
Progress: Parameterizing connections
|
|
Progress: Validating
|
|
Progress: Done reading input file
|
|
Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH
|
|
Info: rs232_0: Starting Generation of RS232 UART
|
|
Error: rs232_0: The input clock frequency must be known at generation time.
|
|
Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0"
|
|
Info: uart_screen: Done "uart_screen" with 2 modules, 6 files
|
|
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
|
|
Info: Finished: Create HDL design files for synthesis
|