78 lines
1 KiB
Verilog
78 lines
1 KiB
Verilog
module jyh_4490_6_entry(code, seg, clk_50m, en, in,
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//数码管型码 数码管位码 50M 使能信号 按键
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out0, cnt, subclk);
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//计数值 消抖值
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output [6:0] code;
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output [7:0] seg;
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input en,clk_50m,in;
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output subclk;
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output [3:0] out0;
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output [19:0] cnt;
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wire freshclk;
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wire [3:0] out1;
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wire [3:0] out2;
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wire [3:0] out3;
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wire co,co2,co3;
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reg upd;
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initial begin
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upd=1;
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end
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//分频器
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jyh_4490_6_divider D1(
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.clk(clk_50m),
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.clk_out(freshclk)
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);
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//个位计数器
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jyh_4490_6_counter C1(
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.Q(out0),
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.clk(subclk),
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.en(en),
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.co(co),
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.upd(upd));
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jyh_4490_6_counter C2(
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.Q(out1),
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.clk(co),
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.co(co2),
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.en(en),
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.upd(upd));
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jyh_4490_6_counter C3(
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.Q(out2),
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.clk(co2),
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.co(co3),
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.en(en),
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.upd(upd));
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jyh_4490_6_counter C4(
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.Q(out3),
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.clk(co3),
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.en(en),
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.upd(upd));
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//四位数码管译码器
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jyh_4490_4_encoder E1(
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.codeout(code),
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.d1(out0),
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.d2(out1),
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.d3(out2),
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.d4(out3),
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.clk(freshclk),
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.sel(seg[3:0])
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);
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//消抖模块
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jyh_4490_mstate M1(
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.clk(clk_50m),
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.in(in),
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.en(en),
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.out(subclk),
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.cnt(cnt)
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);
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endmodule
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