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justhomework/Quartus/v4/jyh_4490_4_divider.v
2022-04-12 22:26:39 +08:00

19 lines
No EOL
380 B
Verilog

module jyh_4490_4_divider(clk,clk_out);
input clk;
output reg clk_out;
// localparam TARGET=100000;
localparam TARGET=1;
reg [19:0]counter=0;
initial begin
clk_out=0;
end
always @(posedge clk)
begin
counter=counter+1;
if(counter==TARGET)
begin
counter=0;
clk_out=!clk_out;
end
end
endmodule