64 lines
No EOL
1 KiB
Verilog
64 lines
No EOL
1 KiB
Verilog
//七段四位译码器
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module jyh_4490_3_encoder(sel,codeout,clk, d1, d2, d3, d4);
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input clk;
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input [6:0] d1, d2, d3, d4;
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output reg [3:0] sel; //位选
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output reg [6:0] codeout; //型码
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//当前位置数字
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reg [6:0] code_loc=2'b01;
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//实验性消影
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reg isEnable;
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reg [1:0] loc;
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//循环移位
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always @(posedge clk)
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begin
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if(isEnable)
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isEnable<=0;
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else
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begin
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isEnable<=1;
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if(loc==2'b01)
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loc=2'b10;
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else
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loc=2'b01;
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end
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end
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always @(*)
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begin
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if(isEnable)
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begin
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case (loc)
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2'b01: begin code_loc = d1; sel = 4'b10; end
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2'b10: begin code_loc = d2; sel = 4'b01; end
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endcase
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end
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end
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always @(*)
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begin
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if(isEnable)
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begin
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case (code_loc)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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else
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codeout=7'b0;
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end
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endmodule |