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justhomework/Quartus/v3/jyh_4490_3_entry.v

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module jyh_4490_3_entry(out1, out0, code, sel, CO,
// 十位输出 个位输出 数码管型码 数码管位码 /借位标志位
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in1, in0, load, clk, clk2, clr, en, upd);
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// 十位装载 个位装载 装载信号 计数时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
output [3:0] out1;
output [3:0] out0;
output [6:0] code;
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output [7:0] sel;
output CO;
input [3:0] in1;
input [3:0] in0;
input clk,load,clr,en,upd,clk2;
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wire subclk;
jyh_4490_3_divide(
.clkin(clk),
.clkout(subclk)
);
//个位计数器
jyh_4490_3_counter c0(
.Q(out0),
.clk(clk),
.co(CO),
.clr(clr),
.load(load),
.in(in0),
.en(en),
.upd(upd));
//十位计数器
jyh_4490_3_counter c1(
.Q(out1),
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.clk(CO||load),
.clr(clr),
.load(load),
.in(in1),
.en(en),
.upd(upd));
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//四位数码管译码器
jyh_4490_3_encoder e1(
.codeout(code),
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.d1(out0),
.d2(out1),
.clk(clk2),
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.sel(sel[1:0])
);
endmodule