大概差不多
This commit is contained in:
iridiumR
parent
60050e5fba
commit
453edfb17a
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@ -25,6 +25,7 @@ quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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@ -48,6 +49,7 @@ quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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@ -436,7 +438,7 @@ SIGNAL("code[0]")
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PARENT = "code";
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}
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SIGNAL("seg")
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SIGNAL("sel")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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@ -446,24 +448,24 @@ SIGNAL("seg")
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PARENT = "";
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}
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SIGNAL("seg[1]")
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SIGNAL("sel[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "seg";
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PARENT = "sel";
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}
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SIGNAL("seg[0]")
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SIGNAL("sel[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "seg";
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PARENT = "sel";
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}
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TRANSITION_LIST("clk")
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@ -485,9 +487,9 @@ TRANSITION_LIST("clr")
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 370.0;
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LEVEL 1 FOR 260.0;
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LEVEL 0 FOR 30.0;
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LEVEL 1 FOR 600.0;
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LEVEL 1 FOR 710.0;
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}
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}
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@ -578,9 +580,9 @@ TRANSITION_LIST("load")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 220.0;
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LEVEL 1 FOR 50.0;
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LEVEL 0 FOR 730.0;
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LEVEL 0 FOR 370.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 610.0;
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}
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}
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@ -752,7 +754,7 @@ TRANSITION_LIST("code[0]")
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}
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}
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TRANSITION_LIST("seg[1]")
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TRANSITION_LIST("sel[1]")
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{
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NODE
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{
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@ -761,7 +763,7 @@ TRANSITION_LIST("seg[1]")
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}
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}
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TRANSITION_LIST("seg[0]")
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TRANSITION_LIST("sel[0]")
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{
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NODE
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{
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@ -1115,8 +1117,8 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "seg";
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EXPAND_STATUS = EXPANDED;
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CHANNEL = "sel";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 35;
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TREE_LEVEL = 0;
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@ -1125,7 +1127,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "seg[1]";
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CHANNEL = "sel[1]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 36;
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@ -1135,7 +1137,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "seg[0]";
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CHANNEL = "sel[0]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 37;
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@ -80,4 +80,14 @@ set_global_assignment -name VERILOG_FILE jyh_4490_3_encoder.v
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_global_assignment -name VERILOG_FILE jyh_4490_3_counter.v
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set_global_assignment -name VERILOG_FILE jyh_4490_3_entry.v
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set_location_assignment PIN_88 -to clk2
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set_location_assignment PIN_112 -to code[6]
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set_location_assignment PIN_100 -to code[5]
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set_location_assignment PIN_104 -to code[4]
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set_location_assignment PIN_111 -to code[3]
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set_location_assignment PIN_106 -to code[2]
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set_location_assignment PIN_110 -to code[1]
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set_location_assignment PIN_103 -to code[0]
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set_location_assignment PIN_126 -to sel[1]
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set_location_assignment PIN_119 -to sel[0]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,57 +1,49 @@
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module jyh_4490_3_encoder(codeout,indec,indec2,clk,seg);
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input[3:0] indec,indec2;
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input clk;
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output reg [1:0] seg=2'b01;
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output reg [6:0] codeout;
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reg n = 1;
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always @ (posedge clk)
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begin
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if(n==1)
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begin
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n<=2;
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if(seg==2'b01)
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begin
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case (indec)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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if(seg==2'b10)
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begin
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case (indec2)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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end
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if(n==2)
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begin
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n<=1;
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codeout<=7'b0;
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if(seg==2'b10)
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seg<=2'b01;
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else if(seg==2'b10)
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seg<=2'b01;
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end
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//七段四位译码器
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module jyh_4490_3_encoder(sel,codeout,clk, d1, d2, d3, d4);
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input clk;
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input [6:0] d1, d2, d3, d4;
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output reg [3:0] sel; //位选
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output reg [6:0] codeout; //型码
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//当前位置数字
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reg [6:0] code_loc=2'B01;
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reg [1:0] loc;
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//循环移位
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always @(posedge clk)
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begin
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if(loc==2'b01)
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loc=2'b10;
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else
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loc=2'b01;
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end
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always @(*)
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begin
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sel = 4'b0000;
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case (loc)
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2'b01: begin code_loc = d1; sel = 4'b10; end
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2'b10: begin code_loc = d2; sel = 4'b01; end
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endcase
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end
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always @(*)
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begin
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case (code_loc)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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endmodule
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@ -1,12 +1,12 @@
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module jyh_4490_3_entry(out1, out0, code, seg, CO,
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module jyh_4490_3_entry(out1, out0, code, sel, CO,
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// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
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in1, in0, load, clk, clk2, clr, en, upd);
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// 十位装载 个位装载 装载信号 时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
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in1, in0, load, clk, clk2, clr, en, upd);
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// 十位装载 个位装载 装载信号 计数时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
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output [3:0] out1;
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output [3:0] out0;
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output [6:0] code;
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output [1:0] seg;
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output [1:0] sel;
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output CO;
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input [3:0] in1;
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input [3:0] in0;
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@ -33,12 +33,13 @@ jyh_4490_3_counter c1(
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.en(en),
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.upd(upd));
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//四位数码管译码器
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jyh_4490_3_encoder e1(
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.codeout(code),
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.indec(out0),
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.indec2(out1),
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.d1(out0),
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.d2(out1),
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.clk(clk2),
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.seg(seg)
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.sel(sel)
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);
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endmodule
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