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大概差不多

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iridiumR 2022-04-05 17:15:28 +08:00
parent 60050e5fba
commit 453edfb17a
4 changed files with 83 additions and 78 deletions
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34
Quartus/v3/Waveform.vwf
View file

@ -25,6 +25,7 @@ quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
@ -48,6 +49,7 @@ quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
@ -436,7 +438,7 @@ SIGNAL("code[0]")
PARENT = "code";
}
SIGNAL("seg")
SIGNAL("sel")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
@ -446,24 +448,24 @@ SIGNAL("seg")
PARENT = "";
}
SIGNAL("seg[1]")
SIGNAL("sel[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "seg";
PARENT = "sel";
}
SIGNAL("seg[0]")
SIGNAL("sel[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "seg";
PARENT = "sel";
}
TRANSITION_LIST("clk")
@ -485,9 +487,9 @@ TRANSITION_LIST("clr")
NODE
{
REPEAT = 1;
LEVEL 1 FOR 370.0;
LEVEL 1 FOR 260.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 600.0;
LEVEL 1 FOR 710.0;
}
}
@ -578,9 +580,9 @@ TRANSITION_LIST("load")
NODE
{
REPEAT = 1;
LEVEL 0 FOR 220.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 730.0;
LEVEL 0 FOR 370.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 610.0;
}
}
@ -752,7 +754,7 @@ TRANSITION_LIST("code[0]")
}
}
TRANSITION_LIST("seg[1]")
TRANSITION_LIST("sel[1]")
{
NODE
{
@ -761,7 +763,7 @@ TRANSITION_LIST("seg[1]")
}
}
TRANSITION_LIST("seg[0]")
TRANSITION_LIST("sel[0]")
{
NODE
{
@ -1115,8 +1117,8 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "seg";
EXPAND_STATUS = EXPANDED;
CHANNEL = "sel";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 35;
TREE_LEVEL = 0;
@ -1125,7 +1127,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "seg[1]";
CHANNEL = "sel[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 36;
@ -1135,7 +1137,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "seg[0]";
CHANNEL = "sel[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 37;

10
Quartus/v3/jyh_4490_3.qsf
View file

@ -80,4 +80,14 @@ set_global_assignment -name VERILOG_FILE jyh_4490_3_encoder.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VERILOG_FILE jyh_4490_3_counter.v
set_global_assignment -name VERILOG_FILE jyh_4490_3_entry.v
set_location_assignment PIN_88 -to clk2
set_location_assignment PIN_112 -to code[6]
set_location_assignment PIN_100 -to code[5]
set_location_assignment PIN_104 -to code[4]
set_location_assignment PIN_111 -to code[3]
set_location_assignment PIN_106 -to code[2]
set_location_assignment PIN_110 -to code[1]
set_location_assignment PIN_103 -to code[0]
set_location_assignment PIN_126 -to sel[1]
set_location_assignment PIN_119 -to sel[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

102
Quartus/v3/jyh_4490_3_encoder.v
View file

@ -1,57 +1,49 @@
module jyh_4490_3_encoder(codeout,indec,indec2,clk,seg);
input[3:0] indec,indec2;
input clk;
output reg [1:0] seg=2'b01;
output reg [6:0] codeout;
reg n = 1;
always @ (posedge clk)
begin
if(n==1)
begin
n<=2;
if(seg==2'b01)
begin
case (indec)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
if(seg==2'b10)
begin
case (indec2)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
end
if(n==2)
begin
n<=1;
codeout<=7'b0;
if(seg==2'b10)
seg<=2'b01;
else if(seg==2'b10)
seg<=2'b01;
end
//七段四位译码器
module jyh_4490_3_encoder(sel,codeout,clk, d1, d2, d3, d4);
input clk;
input [6:0] d1, d2, d3, d4;
output reg [3:0] sel; //位选
output reg [6:0] codeout; //型码
//当前位置数字
reg [6:0] code_loc=2'B01;
reg [1:0] loc;
//循环移位
always @(posedge clk)
begin
if(loc==2'b01)
loc=2'b10;
else
loc=2'b01;
end
always @(*)
begin
sel = 4'b0000;
case (loc)
2'b01: begin code_loc = d1; sel = 4'b10; end
2'b10: begin code_loc = d2; sel = 4'b01; end
endcase
end
always @(*)
begin
case (code_loc)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
endmodule

15
Quartus/v3/jyh_4490_3_entry.v
View file

@ -1,12 +1,12 @@
module jyh_4490_3_entry(out1, out0, code, seg, CO,
module jyh_4490_3_entry(out1, out0, code, sel, CO,
// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
in1, in0, load, clk, clk2, clr, en, upd);
// 十位装载 个位装载 装载信号 时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
in1, in0, load, clk, clk2, clr, en, upd);
// 十位装载 个位装载 装载信号 计数时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
output [3:0] out1;
output [3:0] out0;
output [6:0] code;
output [1:0] seg;
output [1:0] sel;
output CO;
input [3:0] in1;
input [3:0] in0;
@ -33,12 +33,13 @@ jyh_4490_3_counter c1(
.en(en),
.upd(upd));
//四位数码管译码器
jyh_4490_3_encoder e1(
.codeout(code),
.indec(out0),
.indec2(out1),
.d1(out0),
.d2(out1),
.clk(clk2),
.seg(seg)
.sel(sel)
);
endmodule