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justhomework/Quartus/v3/jyh_4490_3_encoder.v
2022-04-05 17:15:28 +08:00

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Verilog

//七段四位译码器
module jyh_4490_3_encoder(sel,codeout,clk, d1, d2, d3, d4);
input clk;
input [6:0] d1, d2, d3, d4;
output reg [3:0] sel; //位选
output reg [6:0] codeout; //型码
//当前位置数字
reg [6:0] code_loc=2'B01;
reg [1:0] loc;
//循环移位
always @(posedge clk)
begin
if(loc==2'b01)
loc=2'b10;
else
loc=2'b01;
end
always @(*)
begin
sel = 4'b0000;
case (loc)
2'b01: begin code_loc = d1; sel = 4'b10; end
2'b10: begin code_loc = d2; sel = 4'b01; end
endcase
end
always @(*)
begin
case (code_loc)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
endmodule