justhomework/Quartus/v6/jyh_4490_6.qsf

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# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 21:39:46  五月 09, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
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# 1) The default values for assignments are stored in the file:
#		jyh_4490_6_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
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set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_6_entry
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:39:46  五月 09, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name VERILOG_FILE jyh_4490_mstate.v
set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench.v
set_global_assignment -name VERILOG_FILE jyh_4490_6_counter.v
set_global_assignment -name VERILOG_FILE jyh_4490_6_encoder.v
set_global_assignment -name VERILOG_FILE jyh_4490_6_entry.v
set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench_top.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE jyh_4490_6_divider.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top