justhomework/Quartus/v2/jyh_4490_2_1.v

//计数器模块
module jyh_4490_2_1(clk,en,Q);
input clk,en;
output reg[2:0] Q;

always@(posedge clk)
begin
	if(en == 1'b1)
	begin
		if(Q<3'd6)
		Q <= Q + 1'b1;
		else
		Q <= 0;
	end
	else
	Q<=0;
end
endmodule