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justhomework/Quartus/v6_testbench/transcript

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# Compile of jyh_4490_6_testbench.v was successful.
vsim work.jyh_4490_6_testbench
# vsim work.jyh_4490_6_testbench
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# Start time: 18:05:59 on May 10,2022
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# Loading work.jyh_4490_6_testbench
# Loading work.jyh_4490_mstate
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4.
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 40
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(40): [TFMPC] - Missing connection for port 'en'.
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add wave -position end sim:/jyh_4490_6_testbench/clk
add wave -position end sim:/jyh_4490_6_testbench/in
add wave -position end sim:/jyh_4490_6_testbench/en
add wave -position end sim:/jyh_4490_6_testbench/out
add wave -position end sim:/jyh_4490_6_testbench/cnt
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run -continue
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run -all
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# Break key hit
# Simulation stop requested.
# End time: 18:28:16 on May 10,2022, Elapsed time: 0:22:17
# Errors: 0, Warnings: 6