30 lines
427 B
Coq
30 lines
427 B
Coq
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module mstate(clk,key,out);
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input clk,key;
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output reg[2:0] out;
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reg[1:0] state;
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parameter s0=0,s1=1,s2=2;
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initial begin
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state=s0;
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end
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always @(posedge clk)
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case (state)
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s0:if(key) state=s0;
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else state=s1;
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s1:if(key) state=s1;
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else state=s2;
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s2:if(key) state=s2;
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else state=s0;
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default: state=s0;
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endcase
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always
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case (state)
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s0:out<=3'b001;
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s1:out<=3'b010;
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s2:out<=3'b100;
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default:out<=3'b001;
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endcase
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endmodule
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