93 lines
3.8 KiB
Text
93 lines
3.8 KiB
Text
|
# Compile of jyh_4490_6_testbench.v was successful.
|
||
|
|
# Compile of jyh_4490_mstate.v was successful.
|
||
|
|
# 2 compiles, 0 failed with no errors.
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# vsim work.jyh_4490_6_testbench
|
||
|
|
# Start time: 23:55:10 on May 09,2022
|
||
|
|
# Loading work.jyh_4490_6_testbench
|
||
|
|
# Loading work.jyh_4490_mstate
|
||
|
|
# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'.
|
||
|
|
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39
|
||
|
|
# Error loading design
|
||
|
|
# End time: 23:55:10 on May 09,2022, Elapsed time: 0:00:00
|
||
|
|
# Errors: 1, Warnings: 7
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# vsim work.jyh_4490_6_testbench
|
||
|
|
# Start time: 23:55:11 on May 09,2022
|
||
|
|
# Loading work.jyh_4490_6_testbench
|
||
|
|
# Loading work.jyh_4490_mstate
|
||
|
|
# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'.
|
||
|
|
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39
|
||
|
|
# Error loading design
|
||
|
|
# End time: 23:55:11 on May 09,2022, Elapsed time: 0:00:00
|
||
|
|
# Errors: 1, Warnings: 1
|
||
|
|
# can't read "Startup(-L)": no such element in array
|
||
|
|
# Load canceled
|
||
|
|
# Compile of jyh_4490_6_testbench.v failed with 1 errors.
|
||
|
|
# Compile of jyh_4490_6_testbench.v was successful.
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# vsim work.jyh_4490_6_testbench
|
||
|
|
# Start time: 23:57:01 on May 09,2022
|
||
|
|
# Loading work.jyh_4490_6_testbench
|
||
|
|
# Loading work.jyh_4490_mstate
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/clk
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/clr
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/in
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/out
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/cnt
|
||
|
|
run -all
|
||
|
|
# Compile of jyh_4490_6_testbench.v was successful.
|
||
|
|
# Compile of jyh_4490_mstate.v was successful.
|
||
|
|
# 2 compiles, 0 failed with no errors.
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# End time: 23:59:24 on May 09,2022, Elapsed time: 0:02:23
|
||
|
|
# Errors: 0, Warnings: 4
|
||
|
|
# vsim work.jyh_4490_6_testbench
|
||
|
|
# Start time: 23:59:24 on May 09,2022
|
||
|
|
# Loading work.jyh_4490_6_testbench
|
||
|
|
# Loading work.jyh_4490_mstate
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/clk
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/in
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/out
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/cnt
|
||
|
|
run -all
|
||
|
|
# Compile of jyh_4490_6_testbench.v was successful.
|
||
|
|
# Compile of jyh_4490_mstate.v was successful.
|
||
|
|
# 2 compiles, 0 failed with no errors.
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# running
|
||
|
|
vsim work.jyh_4490_6_testbench
|
||
|
|
# End time: 00:03:02 on May 10,2022, Elapsed time: 0:03:38
|
||
|
|
# Errors: 0, Warnings: 2
|
||
|
|
# vsim work.jyh_4490_6_testbench
|
||
|
|
# Start time: 00:03:02 on May 10,2022
|
||
|
|
# Loading work.jyh_4490_6_testbench
|
||
|
|
# Loading work.jyh_4490_mstate
|
||
|
|
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4.
|
||
|
|
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 38
|
||
|
|
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(38): [TFMPC] - Missing connection for port 'en'.
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/clk
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/in
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/en
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/out
|
||
|
|
add wave -position end sim:/jyh_4490_6_testbench/cnt
|
||
|
|
run -all
|
||
|
|
# Break key hit
|
||
|
|
# Simulation stop requested.
|
||
|
|
# End time: 00:05:02 on May 10,2022, Elapsed time: 0:02:00
|
||
|
|
# Errors: 0, Warnings: 4
|