73 lines
3.6 KiB
Text
73 lines
3.6 KiB
Text
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2021 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
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# Date created = 21:26:12 三月 29, 2022
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# jyh_4490_2_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Intel recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE6E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY v2_entry_4490
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:26:12 三月 29, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name VERILOG_FILE v2_entry_4490.v
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set_global_assignment -name VERILOG_FILE jyh_4490_2_2.v
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set_global_assignment -name VERILOG_FILE jyh_4490_2_1.v
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_location_assignment PIN_31 -to enable_in
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set_location_assignment PIN_46 -to Qout[0]
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set_location_assignment PIN_50 -to Qout[1]
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set_location_assignment PIN_52 -to Qout[2]
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set_location_assignment PIN_88 -to clk_in
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set_location_assignment PIN_43 -to code_out[6]
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set_location_assignment PIN_44 -to code_out[5]
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set_location_assignment PIN_39 -to code_out[4]
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set_location_assignment PIN_42 -to code_out[3]
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set_location_assignment PIN_32 -to code_out[2]
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set_location_assignment PIN_33 -to code_out[1]
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set_location_assignment PIN_30 -to code_out[0]
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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