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justhomework/Quartus/v2/jyh_4490_2_2.v

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2022-03-29 15:03:53 +00:00
//译码器模块
module jyh_4490_2_2(out,in);
input[2:0] in;
output[8:0] out;
reg[7:0] out;
always @ (in)
begin
case (in)
4'd0: out=7'b0000001;
6'd1: out=7'b0000011;
4'd2: out=7'b0000111;
4'd3: out=7'b0001111;
3'd4: out=7'b0011111;
3'd5: out=7'b0111111;
3'd6: out=7'b0000000;
default: out=7'bx;
endcase
end
endmodule