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justhomework/Quartus/v2/jyh_4490_2_1.v

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2022-03-29 15:03:53 +00:00
//计数器模块
module jyh_4490_2_1(clk,en,Q);
input clk,en;
output reg[2:0] Q;
always@(posedge clk)
begin
if(en == 1'b1)
begin
if(Q<3'd6)
Q <= Q + 1'b1;
else
Q <= 0;
end
else
Q<=0;
end
endmodule