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justhomework/Quartus/v4/jyh_4490_4_entry.v

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module jyh_4490_4_entry(out1, out0, code, sel, CO,
// 十位输出 个位输出 数码管型码 数码管位码 /借位标志位
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in1, in0, load, clk, subclk, clr, en, upd);
// 十位装载 个位装载 装载信号 计数时钟信号 分频信号 清零信号 使能信号 正反计数标志位
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output [3:0] out1;
output [3:0] out0;
output [6:0] code;
output [7:0] sel;
output CO;
input [3:0] in1;
input [3:0] in0;
input clk,load,clr,en,upd;
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//分频器
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output subclk;
jyh_4490_4_divider D1(
.clk(clk),
.clk_out(subclk)
);
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//个位计数器
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jyh_4490_4_counter C1(
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.Q(out0),
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.clk(subclk),
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.co(CO),
.clr(clr),
.load(load),
.in(in0),
.en(en),
.upd(upd));
//十位计数器
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jyh_4490_4_counter C2(
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.Q(out1),
.clk(CO||load),
.clr(clr),
.load(load),
.en(en),
.upd(upd));
//四位数码管译码器
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jyh_4490_4_encoder E1(
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.codeout(code),
.d1(out0),
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.d2(out1),
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.clk(clk),
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.sel(sel[3:0])
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);
endmodule