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直接搬过来了

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iridiumR 2022-04-12 16:39:06 +08:00
parent 9aa7446b7c
commit 130d8e43d5
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31
Quartus/v4/jyh_4490_4.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 16:30:41 四月 12, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "21.1"
DATE = "16:30:41 四月 12, 2022"
# Revisions
PROJECT_REVISION = "jyh_4490_4"

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Quartus/v4/jyh_4490_4.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 16:30:41 四月 12, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# jyh_4490_4_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_4_entry
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:30:41 四月 12, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name VERILOG_FILE jyh_4490_4_simpleEncoder.v
set_global_assignment -name VERILOG_FILE jyh_4490_4_entry.v
set_global_assignment -name VERILOG_FILE jyh_4490_4_encoder.v
set_global_assignment -name VERILOG_FILE jyh_4490_4_counter.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Quartus/v4/jyh_4490_4_counter.v Normal file
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module jyh_4490_4_counter(Q,clk,clr,load,in,en,upd,co);
input[3:0] in;
input en,clk,clr,load,upd;
output reg [3:0] Q;
output reg co;
reg co_flag;
always@(posedge clk,negedge clr)
begin
//异步清零
if(!clr)
Q<=0;
else if(en)
begin
//同步置数
if(load)
begin
Q<=in;
end
else if(co_flag)
begin
co<=1;
co_flag=0;
end
else if(!co_flag)
co<=0;
//正反计数
if(upd)
begin
if(Q>=4'd9)
begin
Q<=4'd0;
co_flag=1;
end
else
begin
Q <= Q+1;
end
end
else
begin
if(Q<=4'd0)
begin
Q<=4'd9;
end
else if(Q==4'd1)
begin
Q <= Q-1;
co_flag=1;
end
else
begin
Q <= Q-1;
end
end
end
else
Q<=0;
end
endmodule

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Quartus/v4/jyh_4490_4_encoder.v Normal file
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//七段四位译码器
module jyh_4490_4_encoder(sel,codeout,clk, d1, d2);
input clk;
input [6:0] d1, d2;
output reg [1:0] sel; //位选
output reg [6:0] codeout; //型码
//当前位置数字
reg [6:0] code_loc=2'b01;
//实验性消影
reg isEnable;
reg [1:0] loc;
//循环移位
always @(posedge clk)
begin
if(isEnable)
isEnable<=0;
else
begin
isEnable<=1;
if(loc==2'b01)
loc=2'b10;
else
loc=2'b01;
end
end
always @(*)
begin
if(isEnable)
begin
case (loc)
2'b01: begin code_loc = d1; sel = 4'b10; end
2'b10: begin code_loc = d2; sel = 4'b01; end
endcase
end
end
always @(*)
begin
if(isEnable)
begin
case (code_loc)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
else
codeout=7'b0;
end
endmodule

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module jyh_4490_4_entry(out1, out0, code, sel, CO,
// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
in1, in0, load, clk, clr, en, upd);
// 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位
output [3:0] out1;
output [3:0] out0;
output [6:0] code;
output [7:0] sel;
output CO;
input [3:0] in1;
input [3:0] in0;
input clk,load,clr,en,upd;
//wire subclk;
//jyh_4490_3_divide(
//.clkin(clk),
//.clkout(subclk)
//);
//个位计数器
jyh_4490_4_counter c0(
.Q(out0),
.clk(clk),
.co(CO),
.clr(clr),
.load(load),
.in(in0),
.en(en),
.upd(upd));
//十位计数器
jyh_4490_4_counter c1(
.Q(out1),
.clk(CO||load),
.clr(clr),
.load(load),
.in(in1),
.en(en),
.upd(upd));
//四位数码管译码器
//jyh_4490_3_encoder e1(
//.codeout(code),
//.d1(out0),
//.d2(out1),
//.clk(clk),
//.sel(sel[1:0])
//);
jyh_4490_4_simpleEncoder e1(
.codeout(code),
.d1(out0),
.clk(clk),
.sel(sel[0:0])
);
endmodule

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//七段一位译码器
module jyh_4490_4_simpleEncoder(sel,codeout,clk, d1);
input clk;
input [6:0] d1;
output reg sel; //位选
output reg [6:0] codeout; //型码
always @(clk)
begin
case (d1)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
endmodule