实验7

Quartus/v7/jyh_4490_7.qsf

@@ -56,4 +56,10 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VERILOG_FILE jyh_4490_7_testbench.v
 set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_location_assignment PIN_90 -to clk
+set_location_assignment PIN_23 -to f0
+set_location_assignment PIN_46 -to f1
+set_location_assignment PIN_50 -to f2
+set_location_assignment PIN_24 -to p
+set_location_assignment PIN_31 -to sta
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/v7_testbench/jyh_4490_7.cr.mti

@@ -1,4 +1,11 @@
-/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
+/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_7_is
+
+Top level modules:
+	jyh_4490_7_is
+
+} {} {}} /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
 Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
 -- Compiling module jyh_4490_7_testbench
 

Quartus/v7_testbench/jyh_4490_7.mpf

@@ -413,7 +413,7 @@ Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 2
 Project_File_0 = /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
-Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1652793275 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652796099 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_1 = /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
 Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652794988 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 1

Quartus/v7_testbench/transcript

@@ -11,3 +11,27 @@ add wave -position end  sim:/jyh_4490_7_testbench/f2
 add wave -position end  sim:/jyh_4490_7_testbench/p
 add wave -position end  sim:/jyh_4490_7_testbench/sta
 run -all
+# Compile of jyh_4490_7_is.v was successful.
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+vsim work.jyh_4490_7_testbench
+# running
+restart -f
+# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
+# Loading work.jyh_4490_7_is
+restart
+run -all
+# End time: 22:26:44 on May 17,2022, Elapsed time: 0:43:03
+# Errors: 0, Warnings: 1

Quartus/v7_testbench/work/_info

@@ -10,23 +10,23 @@ z2
 cModel Technology
 d/home/ir
 vjyh_4490_7_is
-!s110 1652794566
+!s110 1652796112
 !i10b 1
-!s100 Ch8NYc=4G@_6A9YaMMBnW2
+!s100 RiPFeLFfjmF7=E=:LFh]K1
 Z0 !s11b Dg1SIo80bB@j0V0VzS_@n1
-IBT5^kcKVcE01P1:cX?C;^2
+In?ifFD9`L[n0MW4oMLaTG3
 Z1 VDg1SIo80bB@j0V0VzS_@n1
 Z2 d/home/ir/Documents/codelib/Quartus/v7_testbench
-w1652793275
+w1652796099
 8/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
 F/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
-!i122 0
+!i122 3
-L0 1 79
+L0 1 89
 Z3 OV;L;2020.1;71
 r1
 !s85 0
 31
-!s108 1652794566.000000
+!s108 1652796112.000000
 !s107 /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v|
 !s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v|
 !i113 1