Merge branch 'main' of github.com:iridiumR/justhomework
This commit is contained in:
iridiumR
commit
1862276ba6
13 changed files with 485 additions and 145 deletions
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@ -20,13 +20,6 @@ proc simTimestamp {} {
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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@ -45,13 +38,6 @@ proc simTimestamp {} {
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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@ -350,16 +336,6 @@ SIGNAL("CO")
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PARENT = "";
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}
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SIGNAL("clk2")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("code")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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@ -489,9 +465,7 @@ TRANSITION_LIST("clr")
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 260.0;
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LEVEL 0 FOR 30.0;
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LEVEL 1 FOR 710.0;
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LEVEL 1 FOR 1000.0;
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}
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}
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@ -500,8 +474,7 @@ TRANSITION_LIST("en")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 20.0;
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LEVEL 1 FOR 980.0;
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LEVEL 1 FOR 1000.0;
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}
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}
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@ -582,9 +555,7 @@ TRANSITION_LIST("load")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 370.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 610.0;
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LEVEL 0 FOR 1000.0;
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}
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}
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@ -665,8 +636,8 @@ TRANSITION_LIST("upd")
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 150.0;
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LEVEL 1 FOR 850.0;
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LEVEL 0 FOR 500.0;
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LEVEL 1 FOR 500.0;
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}
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}
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@ -679,20 +650,6 @@ TRANSITION_LIST("CO")
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}
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}
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TRANSITION_LIST("clk2")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 200;
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LEVEL 0 FOR 2.5;
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LEVEL 1 FOR 2.5;
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}
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}
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}
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TRANSITION_LIST("code[6]")
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{
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NODE
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@ -785,7 +742,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "clk2";
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CHANNEL = "clr";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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@ -794,7 +751,7 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "clr";
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CHANNEL = "upd";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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@ -803,30 +760,21 @@ DISPLAY_LINE
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DISPLAY_LINE
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{
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CHANNEL = "upd";
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CHANNEL = "en";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 3;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "en";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 4;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "in0";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 5;
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TREE_INDEX = 4;
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TREE_LEVEL = 0;
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CHILDREN = 6, 7, 8, 9;
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CHILDREN = 5, 6, 7, 8;
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}
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DISPLAY_LINE
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@ -834,9 +782,9 @@ DISPLAY_LINE
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CHANNEL = "in0[3]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 6;
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TREE_INDEX = 5;
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TREE_LEVEL = 1;
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PARENT = 5;
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PARENT = 4;
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}
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DISPLAY_LINE
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@ -844,9 +792,9 @@ DISPLAY_LINE
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CHANNEL = "in0[2]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 7;
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TREE_INDEX = 6;
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TREE_LEVEL = 1;
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PARENT = 5;
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PARENT = 4;
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}
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DISPLAY_LINE
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@ -854,9 +802,9 @@ DISPLAY_LINE
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CHANNEL = "in0[1]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 8;
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TREE_INDEX = 7;
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TREE_LEVEL = 1;
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PARENT = 5;
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PARENT = 4;
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}
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DISPLAY_LINE
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@ -864,9 +812,9 @@ DISPLAY_LINE
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CHANNEL = "in0[0]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 9;
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TREE_INDEX = 8;
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TREE_LEVEL = 1;
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PARENT = 5;
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PARENT = 4;
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}
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DISPLAY_LINE
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@ -874,9 +822,9 @@ DISPLAY_LINE
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CHANNEL = "in1";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 10;
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TREE_INDEX = 9;
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TREE_LEVEL = 0;
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CHILDREN = 11, 12, 13, 14;
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CHILDREN = 10, 11, 12, 13;
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}
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DISPLAY_LINE
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@ -884,9 +832,9 @@ DISPLAY_LINE
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CHANNEL = "in1[3]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 11;
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TREE_INDEX = 10;
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TREE_LEVEL = 1;
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PARENT = 10;
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PARENT = 9;
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}
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DISPLAY_LINE
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@ -894,9 +842,9 @@ DISPLAY_LINE
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CHANNEL = "in1[2]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 12;
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TREE_INDEX = 11;
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TREE_LEVEL = 1;
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PARENT = 10;
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PARENT = 9;
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}
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DISPLAY_LINE
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@ -904,9 +852,9 @@ DISPLAY_LINE
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CHANNEL = "in1[1]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 13;
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TREE_INDEX = 12;
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TREE_LEVEL = 1;
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PARENT = 10;
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PARENT = 9;
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}
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DISPLAY_LINE
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@ -914,9 +862,9 @@ DISPLAY_LINE
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CHANNEL = "in1[0]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 14;
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TREE_INDEX = 13;
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TREE_LEVEL = 1;
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PARENT = 10;
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PARENT = 9;
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}
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DISPLAY_LINE
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@ -924,7 +872,7 @@ DISPLAY_LINE
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CHANNEL = "load";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 15;
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TREE_INDEX = 14;
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TREE_LEVEL = 0;
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}
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@ -933,7 +881,7 @@ DISPLAY_LINE
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CHANNEL = "CO";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 16;
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TREE_INDEX = 15;
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TREE_LEVEL = 0;
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}
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@ -942,9 +890,9 @@ DISPLAY_LINE
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CHANNEL = "out0";
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EXPAND_STATUS = EXPANDED;
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RADIX = Unsigned;
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TREE_INDEX = 17;
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TREE_INDEX = 16;
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TREE_LEVEL = 0;
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CHILDREN = 18, 19, 20, 21;
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CHILDREN = 17, 18, 19, 20;
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}
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DISPLAY_LINE
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@ -952,9 +900,9 @@ DISPLAY_LINE
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CHANNEL = "out0[3]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 18;
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TREE_INDEX = 17;
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TREE_LEVEL = 1;
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PARENT = 17;
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PARENT = 16;
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}
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DISPLAY_LINE
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@ -962,9 +910,9 @@ DISPLAY_LINE
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CHANNEL = "out0[2]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 19;
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TREE_INDEX = 18;
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TREE_LEVEL = 1;
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PARENT = 17;
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PARENT = 16;
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}
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DISPLAY_LINE
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@ -972,9 +920,9 @@ DISPLAY_LINE
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CHANNEL = "out0[1]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 20;
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TREE_INDEX = 19;
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TREE_LEVEL = 1;
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PARENT = 17;
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PARENT = 16;
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}
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DISPLAY_LINE
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@ -982,9 +930,9 @@ DISPLAY_LINE
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CHANNEL = "out0[0]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 21;
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TREE_INDEX = 20;
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TREE_LEVEL = 1;
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PARENT = 17;
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PARENT = 16;
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}
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DISPLAY_LINE
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@ -992,9 +940,9 @@ DISPLAY_LINE
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CHANNEL = "out1";
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EXPAND_STATUS = EXPANDED;
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RADIX = Unsigned;
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TREE_INDEX = 22;
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||||
TREE_INDEX = 21;
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TREE_LEVEL = 0;
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||||
CHILDREN = 23, 24, 25, 26;
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CHILDREN = 22, 23, 24, 25;
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}
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DISPLAY_LINE
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@ -1002,9 +950,9 @@ DISPLAY_LINE
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CHANNEL = "out1[3]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 23;
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TREE_INDEX = 22;
|
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TREE_LEVEL = 1;
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PARENT = 22;
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PARENT = 21;
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}
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DISPLAY_LINE
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@ -1012,9 +960,9 @@ DISPLAY_LINE
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CHANNEL = "out1[2]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Unsigned;
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TREE_INDEX = 24;
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TREE_INDEX = 23;
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TREE_LEVEL = 1;
|
||||
PARENT = 22;
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PARENT = 21;
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||||
}
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DISPLAY_LINE
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@ -1022,9 +970,9 @@ DISPLAY_LINE
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CHANNEL = "out1[1]";
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EXPAND_STATUS = COLLAPSED;
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||||
RADIX = Unsigned;
|
||||
TREE_INDEX = 25;
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||||
TREE_INDEX = 24;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 22;
|
||||
PARENT = 21;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
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||||
|
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@ -1032,9 +980,9 @@ DISPLAY_LINE
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|||
CHANNEL = "out1[0]";
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||||
EXPAND_STATUS = COLLAPSED;
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||||
RADIX = Unsigned;
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||||
TREE_INDEX = 26;
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||||
TREE_INDEX = 25;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 22;
|
||||
PARENT = 21;
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||||
}
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||||
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||||
DISPLAY_LINE
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|
@ -1042,9 +990,9 @@ DISPLAY_LINE
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|||
CHANNEL = "code";
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||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 27;
|
||||
TREE_INDEX = 26;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 28, 29, 30, 31, 32, 33, 34;
|
||||
CHILDREN = 27, 28, 29, 30, 31, 32, 33;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
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|
@ -1052,9 +1000,9 @@ DISPLAY_LINE
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|||
CHANNEL = "code[6]";
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||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 28;
|
||||
TREE_INDEX = 27;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
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||||
|
|
@ -1062,9 +1010,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "code[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 29;
|
||||
TREE_INDEX = 28;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1072,9 +1020,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "code[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 30;
|
||||
TREE_INDEX = 29;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1082,9 +1030,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "code[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 31;
|
||||
TREE_INDEX = 30;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1092,9 +1040,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "code[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 32;
|
||||
TREE_INDEX = 31;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1102,9 +1050,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "code[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 33;
|
||||
TREE_INDEX = 32;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1112,9 +1060,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "code[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 34;
|
||||
TREE_INDEX = 33;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 27;
|
||||
PARENT = 26;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1122,9 +1070,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "sel";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 35;
|
||||
TREE_INDEX = 34;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 36, 37;
|
||||
CHILDREN = 35, 36;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1132,9 +1080,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "sel[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 36;
|
||||
TREE_INDEX = 35;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 35;
|
||||
PARENT = 34;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
|
|
@ -1142,9 +1090,9 @@ DISPLAY_LINE
|
|||
CHANNEL = "sel[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 37;
|
||||
TREE_INDEX = 36;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 35;
|
||||
PARENT = 34;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
|
|
|
|||
|
|
@ -88,6 +88,24 @@ set_location_assignment PIN_111 -to code[3]
|
|||
set_location_assignment PIN_106 -to code[2]
|
||||
set_location_assignment PIN_110 -to code[1]
|
||||
set_location_assignment PIN_103 -to code[0]
|
||||
set_location_assignment PIN_126 -to sel[1]
|
||||
set_location_assignment PIN_119 -to sel[0]
|
||||
set_location_assignment PIN_119 -to sel[1]
|
||||
set_location_assignment PIN_126 -to sel[0]
|
||||
set_location_assignment PIN_115 -to sel[2]
|
||||
set_location_assignment PIN_125 -to sel[3]
|
||||
set_location_assignment PIN_114 -to sel[4]
|
||||
set_location_assignment PIN_121 -to sel[5]
|
||||
set_location_assignment PIN_113 -to sel[6]
|
||||
set_location_assignment PIN_120 -to sel[7]
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_3_divide.v
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Precision Synthesis"
|
||||
set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_3_simpleEncoder.v
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
|
@ -5,6 +5,7 @@ input en,clk,clr,load,upd;
|
|||
output reg [3:0] Q;
|
||||
output reg co;
|
||||
|
||||
reg co_flag;
|
||||
|
||||
always@(posedge clk,negedge clr)
|
||||
begin
|
||||
|
|
@ -19,21 +20,25 @@ begin
|
|||
if(load)
|
||||
begin
|
||||
Q<=in;
|
||||
co<=1'b1;
|
||||
end
|
||||
|
||||
else if(co_flag)
|
||||
begin
|
||||
co<=1;
|
||||
co_flag=0;
|
||||
end
|
||||
else if(!co_flag)
|
||||
co<=0;
|
||||
//正反计数
|
||||
else if(upd)
|
||||
if(upd)
|
||||
begin
|
||||
if(Q>=4'd9)
|
||||
begin
|
||||
Q<=4'd0;
|
||||
co<=1'b1;
|
||||
co_flag=1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q <= Q+1;
|
||||
co<=0;
|
||||
end
|
||||
end
|
||||
else
|
||||
|
|
@ -41,12 +46,15 @@ begin
|
|||
if(Q<=4'd0)
|
||||
begin
|
||||
Q<=4'd9;
|
||||
co<=1'b1;
|
||||
end
|
||||
else if(Q==4'd1)
|
||||
begin
|
||||
Q <= Q-1;
|
||||
co_flag=1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q <= Q-1;
|
||||
co<=0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
15
Quartus/v3/jyh_4490_3_divide.v
Normal file
15
Quartus/v3/jyh_4490_3_divide.v
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
module jyh_4490_3_divide(clkin,clkout);
|
||||
input clkin;
|
||||
output reg clkout=0;
|
||||
|
||||
reg [2:0] temp;
|
||||
always@(posedge clkin)
|
||||
begin
|
||||
temp<=temp+1;
|
||||
if(temp==0)
|
||||
clkout=~clkout;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
//七段四位译码器
|
||||
module jyh_4490_3_encoder(sel,codeout,clk, d1, d2, d3, d4);
|
||||
module jyh_4490_3_encoder(sel,codeout,clk, d1, d2);
|
||||
input clk;
|
||||
input [6:0] d1, d2, d3, d4;
|
||||
output reg [3:0] sel; //位选
|
||||
input [6:0] d1, d2;
|
||||
output reg [1:0] sel; //位选
|
||||
output reg [6:0] codeout; //型码
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,16 +1,24 @@
|
|||
module jyh_4490_3_entry(out1, out0, code, sel, CO,
|
||||
// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
|
||||
in1, in0, load, clk, clk2, clr, en, upd);
|
||||
// 十位装载 个位装载 装载信号 计数时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
|
||||
in1, in0, load, clk, clr, en, upd);
|
||||
// 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位
|
||||
|
||||
output [3:0] out1;
|
||||
output [3:0] out0;
|
||||
output [6:0] code;
|
||||
output [1:0] sel;
|
||||
output [7:0] sel;
|
||||
output CO;
|
||||
input [3:0] in1;
|
||||
input [3:0] in0;
|
||||
input clk,load,clr,en,upd,clk2;
|
||||
input clk,load,clr,en,upd;
|
||||
|
||||
|
||||
//wire subclk;
|
||||
//jyh_4490_3_divide(
|
||||
//.clkin(clk),
|
||||
//.clkout(subclk)
|
||||
//);
|
||||
|
||||
|
||||
//个位计数器
|
||||
jyh_4490_3_counter c0(
|
||||
|
|
@ -26,20 +34,29 @@ jyh_4490_3_counter c0(
|
|||
//十位计数器
|
||||
jyh_4490_3_counter c1(
|
||||
.Q(out1),
|
||||
.clk(CO),
|
||||
.clk(CO||load),
|
||||
.clr(clr),
|
||||
.load(load),
|
||||
.in(in1),
|
||||
.en(en),
|
||||
.upd(upd));
|
||||
|
||||
|
||||
|
||||
//四位数码管译码器
|
||||
jyh_4490_3_encoder e1(
|
||||
//jyh_4490_3_encoder e1(
|
||||
//.codeout(code),
|
||||
//.d1(out0),
|
||||
//.d2(out1),
|
||||
//.clk(clk),
|
||||
//.sel(sel[1:0])
|
||||
//);
|
||||
|
||||
jyh_4490_3_simpleEncoder(
|
||||
.codeout(code),
|
||||
.d1(out0),
|
||||
.d2(out1),
|
||||
.clk(clk2),
|
||||
.sel(sel)
|
||||
.clk(clk),
|
||||
.sel(sel[0:0])
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
27
Quartus/v3/jyh_4490_3_simpleEncoder.v
Normal file
27
Quartus/v3/jyh_4490_3_simpleEncoder.v
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
//七段一位译码器
|
||||
module jyh_4490_3_simpleEncoder(sel,codeout,clk, d1);
|
||||
input clk;
|
||||
input [6:0] d1;
|
||||
output reg sel; //位选
|
||||
output reg [6:0] codeout; //型码
|
||||
|
||||
|
||||
|
||||
always @(clk)
|
||||
begin
|
||||
case (d1)
|
||||
4'd0: codeout<=7'b1111110;
|
||||
4'd1: codeout<=7'b0110000;
|
||||
4'd2: codeout<=7'b1101101;
|
||||
4'd3: codeout<=7'b1111001;
|
||||
4'd4: codeout<=7'b0110011;
|
||||
4'd5: codeout<=7'b1011011;
|
||||
4'd6: codeout<=7'b1011111;
|
||||
4'd7: codeout<=7'b1110000;
|
||||
4'd8: codeout<=7'b1111111;
|
||||
4'd9: codeout<=7'b1111011;
|
||||
default: codeout<=7'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
31
Quartus/v4/jyh_4490_4.qpf
Normal file
31
Quartus/v4/jyh_4490_4.qpf
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
# Date created = 16:30:41 四月 12, 2022
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "21.1"
|
||||
DATE = "16:30:41 四月 12, 2022"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "jyh_4490_4"
|
||||
58
Quartus/v4/jyh_4490_4.qsf
Normal file
58
Quartus/v4/jyh_4490_4.qsf
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
# Date created = 16:30:41 四月 12, 2022
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# jyh_4490_4_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Intel recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE6E22C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_4_entry
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:30:41 四月 12, 2022"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_4_simpleEncoder.v
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_4_entry.v
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_4_encoder.v
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_4_counter.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
65
Quartus/v4/jyh_4490_4_counter.v
Normal file
65
Quartus/v4/jyh_4490_4_counter.v
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
module jyh_4490_4_counter(Q,clk,clr,load,in,en,upd,co);
|
||||
|
||||
input[3:0] in;
|
||||
input en,clk,clr,load,upd;
|
||||
output reg [3:0] Q;
|
||||
output reg co;
|
||||
|
||||
reg co_flag;
|
||||
|
||||
always@(posedge clk,negedge clr)
|
||||
begin
|
||||
|
||||
//异步清零
|
||||
if(!clr)
|
||||
Q<=0;
|
||||
|
||||
else if(en)
|
||||
begin
|
||||
//同步置数
|
||||
if(load)
|
||||
begin
|
||||
Q<=in;
|
||||
end
|
||||
else if(co_flag)
|
||||
begin
|
||||
co<=1;
|
||||
co_flag=0;
|
||||
end
|
||||
else if(!co_flag)
|
||||
co<=0;
|
||||
//正反计数
|
||||
if(upd)
|
||||
begin
|
||||
if(Q>=4'd9)
|
||||
begin
|
||||
Q<=4'd0;
|
||||
co_flag=1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q <= Q+1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(Q<=4'd0)
|
||||
begin
|
||||
Q<=4'd9;
|
||||
end
|
||||
else if(Q==4'd1)
|
||||
begin
|
||||
Q <= Q-1;
|
||||
co_flag=1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q <= Q-1;
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
Q<=0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
64
Quartus/v4/jyh_4490_4_encoder.v
Normal file
64
Quartus/v4/jyh_4490_4_encoder.v
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
//七段四位译码器
|
||||
module jyh_4490_4_encoder(sel,codeout,clk, d1, d2);
|
||||
input clk;
|
||||
input [6:0] d1, d2;
|
||||
output reg [1:0] sel; //位选
|
||||
output reg [6:0] codeout; //型码
|
||||
|
||||
|
||||
//当前位置数字
|
||||
reg [6:0] code_loc=2'b01;
|
||||
|
||||
//实验性消影
|
||||
reg isEnable;
|
||||
reg [1:0] loc;
|
||||
|
||||
//循环移位
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(isEnable)
|
||||
isEnable<=0;
|
||||
else
|
||||
begin
|
||||
isEnable<=1;
|
||||
if(loc==2'b01)
|
||||
loc=2'b10;
|
||||
else
|
||||
loc=2'b01;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if(isEnable)
|
||||
begin
|
||||
case (loc)
|
||||
2'b01: begin code_loc = d1; sel = 4'b10; end
|
||||
2'b10: begin code_loc = d2; sel = 4'b01; end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if(isEnable)
|
||||
begin
|
||||
case (code_loc)
|
||||
4'd0: codeout<=7'b1111110;
|
||||
4'd1: codeout<=7'b0110000;
|
||||
4'd2: codeout<=7'b1101101;
|
||||
4'd3: codeout<=7'b1111001;
|
||||
4'd4: codeout<=7'b0110011;
|
||||
4'd5: codeout<=7'b1011011;
|
||||
4'd6: codeout<=7'b1011111;
|
||||
4'd7: codeout<=7'b1110000;
|
||||
4'd8: codeout<=7'b1111111;
|
||||
4'd9: codeout<=7'b1111011;
|
||||
default: codeout<=7'bx;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
codeout=7'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
62
Quartus/v4/jyh_4490_4_entry.v
Normal file
62
Quartus/v4/jyh_4490_4_entry.v
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
module jyh_4490_4_entry(out1, out0, code, sel, CO,
|
||||
// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
|
||||
in1, in0, load, clk, clr, en, upd);
|
||||
// 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位
|
||||
|
||||
output [3:0] out1;
|
||||
output [3:0] out0;
|
||||
output [6:0] code;
|
||||
output [7:0] sel;
|
||||
output CO;
|
||||
input [3:0] in1;
|
||||
input [3:0] in0;
|
||||
input clk,load,clr,en,upd;
|
||||
|
||||
|
||||
//wire subclk;
|
||||
//jyh_4490_3_divide(
|
||||
//.clkin(clk),
|
||||
//.clkout(subclk)
|
||||
//);
|
||||
|
||||
|
||||
//个位计数器
|
||||
jyh_4490_4_counter c0(
|
||||
.Q(out0),
|
||||
.clk(clk),
|
||||
.co(CO),
|
||||
.clr(clr),
|
||||
.load(load),
|
||||
.in(in0),
|
||||
.en(en),
|
||||
.upd(upd));
|
||||
|
||||
//十位计数器
|
||||
jyh_4490_4_counter c1(
|
||||
.Q(out1),
|
||||
.clk(CO||load),
|
||||
.clr(clr),
|
||||
.load(load),
|
||||
.in(in1),
|
||||
.en(en),
|
||||
.upd(upd));
|
||||
|
||||
|
||||
|
||||
//四位数码管译码器
|
||||
//jyh_4490_3_encoder e1(
|
||||
//.codeout(code),
|
||||
//.d1(out0),
|
||||
//.d2(out1),
|
||||
//.clk(clk),
|
||||
//.sel(sel[1:0])
|
||||
//);
|
||||
|
||||
jyh_4490_4_simpleEncoder e1(
|
||||
.codeout(code),
|
||||
.d1(out0),
|
||||
.clk(clk),
|
||||
.sel(sel[0:0])
|
||||
);
|
||||
|
||||
endmodule
|
||||
27
Quartus/v4/jyh_4490_4_simpleEncoder.v
Normal file
27
Quartus/v4/jyh_4490_4_simpleEncoder.v
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
//七段一位译码器
|
||||
module jyh_4490_4_simpleEncoder(sel,codeout,clk, d1);
|
||||
input clk;
|
||||
input [6:0] d1;
|
||||
output reg sel; //位选
|
||||
output reg [6:0] codeout; //型码
|
||||
|
||||
|
||||
|
||||
always @(clk)
|
||||
begin
|
||||
case (d1)
|
||||
4'd0: codeout<=7'b1111110;
|
||||
4'd1: codeout<=7'b0110000;
|
||||
4'd2: codeout<=7'b1101101;
|
||||
4'd3: codeout<=7'b1111001;
|
||||
4'd4: codeout<=7'b0110011;
|
||||
4'd5: codeout<=7'b1011011;
|
||||
4'd6: codeout<=7'b1011111;
|
||||
4'd7: codeout<=7'b1110000;
|
||||
4'd8: codeout<=7'b1111111;
|
||||
4'd9: codeout<=7'b1111011;
|
||||
default: codeout<=7'bx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in a new issue