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Quartus/v7/jyh_4490_7.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2021  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+# Date created = 19:22:48  五月 17, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "21.1"
+DATE = "19:22:48  五月 17, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "jyh_4490_7"

Quartus/v7/jyh_4490_7.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2021  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+# Date created = 19:22:48  五月 17, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		jyh_4490_7_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_7_is
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:22:48  五月 17, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE jyh_4490_7_is.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE jyh_4490_7_testbench.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/v7/jyh_4490_7_is.v

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+module jyh_4490_7_is(f2,f1,f0,clk,p,sta);
+input p,sta,f0,clk;
+output reg f2,f1;
+
+reg flag,flag2;//counter enable flag
+parameter TARGET=15000; //0.3ms
+parameter TARGET2=5000; //0.1ms
+reg [13:0] count;//2^14=16384
+reg [14:0] count2;//2^15=32768
+reg negf0; //whether f0 enter low level
+initial begin
+flag=0;
+flag2=0;
+count=0;
+negf0=0;
+end
+
+always@(posedge clk)
+begin
+	if(!f0)
+		negf0<=1;
+	if(f0&&negf0)
+	begin
+		negf0<=0;
+		flag<=1;
+		flag2<=1;
+		f1<=1;
+		f2<=1;
+	end
+	else
+	begin
+	  //xinchong
+		if(count>=TARGET)
+		begin
+			flag<=0;
+			f1<=0;
+		end
+		
+		//shaochong
+		if(p)
+			if(sta)
+			begin
+				if(count>=5*TARGET2)
+				begin
+					f2<=0;
+					flag2<=0;	
+					//end of a circle
+				end
+				else if(count==4*TARGET2)
+					f2<=1;
+			end
+			if(count>=3*TARGET2)
+			begin
+				f2<=0;
+				if(!sta)
+					flag2<=0;
+					//end of a circle
+			end
+			else if(count>=2*TARGET2)
+				f2<=1;
+			else if(count>=TARGET2)
+				f2<=0;
+		else
+			f2<=f1;
+	
+		
+		//whether to add counter
+		if(flag)
+			count<=count+1;
+		else
+			count<=0;
+		if(flag2)
+			count2<=count+1;
+		else
+			count2<=0;
+	end
+end
+
+endmodule

Quartus/v7/jyh_4490_7_testbench.v

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+`timescale 1ns/1ns
+module jyh_4490_7_testbench;
+wire f1,f2;
+reg clk,f0,p,sta;
+
+initial begin
+clk=0;
+f0=0;
+p=0;
+sta=0;
+end
+
+always #10 clk=~clk;
+always begin    
+
+f0=1;
+#30000;
+f0=0;
+#70000;
+
+f0=1;
+#24000;
+f0=0;
+#76000;
+
+f0=1;
+#18000;
+f0=0;
+#82000;
+
+f0=1;
+#12000;
+f0=0;
+#80000;
+
+f0=1;
+#6000; 
+f0=0;
+#94000;
+
+end
+
+always begin
+p=0;
+sta=0;
+#600000;
+p=1;
+#300000;
+sta=1;
+#300000;
+end
+
+jyh_4490_7_is C0(
+.clk(clk),
+.p(p),
+.f1(f1),
+.f0(f0),
+.sta(sta),
+.f2(f2));
+
+endmodule