61 lines
467 B
Verilog
61 lines
467 B
Verilog
`timescale 1ns/1ns
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module jyh_4490_7_testbench;
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wire f1,f2;
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reg clk,f0,p,sta;
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initial begin
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clk=0;
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f0=0;
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p=0;
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sta=0;
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end
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always #10 clk=~clk;
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always begin
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f0=1;
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#30000;
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f0=0;
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#70000;
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f0=1;
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#24000;
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f0=0;
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#76000;
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f0=1;
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#18000;
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f0=0;
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#82000;
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f0=1;
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#12000;
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f0=0;
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#80000;
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f0=1;
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#6000;
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f0=0;
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#94000;
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end
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always begin
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p=0;
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sta=0;
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#600000;
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p=1;
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#300000;
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sta=1;
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#300000;
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end
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jyh_4490_7_is C0(
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.clk(clk),
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.p(p),
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.f1(f1),
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.f0(f0),
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.sta(sta),
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.f2(f2));
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endmodule
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