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数电实验第二次

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iridiumR 2022-03-30 11:54:43 +08:00
parent d9dab07172
commit 500301993e
1 changed files with 8 additions and 8 deletions
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Quartus/v2/jyh_4490_2_2.v
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//译码器模块 //译码器模块
module jyh_4490_2_2(out,in); module jyh_4490_2_2(out,in);
input[2:0] in; input[2:0] in;
output[8:0] out; output[6:0] out;
reg[7:0] out; reg[7:0] out;
always @ (in) always @ (in)
begin begin
case (in) case (in)
4'd0: out=7'b0000001; 3'd0: out<=7'b0000001;
6'd1: out=7'b0000011; 3'd1: out<=7'b0000011;
4'd2: out=7'b0000111; 3'd2: out<=7'b0000111;
4'd3: out=7'b0001111; 3'd3: out<=7'b0001111;
3'd4: out=7'b0011111; 3'd4: out<=7'b0011111;
3'd5: out=7'b0111111; 3'd5: out<=7'b0111111;
3'd6: out=7'b0000000; 3'd6: out<=7'b0000000;
default: out=7'bx; default: out=7'bx;
endcase endcase