数电实验第一次
This commit is contained in:
iridiumR
parent
b4f3ef2d78
commit
d9dab07172
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@ -0,0 +1,465 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_1 -c jyh_4490_1 --vector_source="/home/ir/Documents/codelib/Quartus/v1/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_1 -c jyh_4490_1 --vector_source="/home/ir/Documents/codelib/Quartus/v1/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/" jyh_4490_1 -c jyh_4490_1</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/" jyh_4490_1 -c jyh_4490_1</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_1.vo
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vlog -work work Waveform.vwf.vt
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vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_1_vlg_vec_tst
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vcd file -direction jyh_4490_1.msim.vcd
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vcd add -internal jyh_4490_1_vlg_vec_tst/*
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vcd add -internal jyh_4490_1_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_1.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_1_vlg_vec_tst
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vcd file -direction jyh_4490_1.msim.vcd
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vcd add -internal jyh_4490_1_vlg_vec_tst/*
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vcd add -internal jyh_4490_1_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("codeout")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 7;
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LSB_INDEX = 0;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("codeout[6]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("codeout[5]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("codeout[4]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("codeout[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("codeout[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("codeout[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("codeout[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "codeout";
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}
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SIGNAL("indec")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 4;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("indec[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "indec";
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}
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SIGNAL("indec[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "indec";
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}
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SIGNAL("indec[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "indec";
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}
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SIGNAL("indec[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "indec";
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}
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TRANSITION_LIST("codeout[6]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("codeout[5]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("codeout[4]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("codeout[3]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("codeout[2]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("codeout[1]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("codeout[0]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("indec[3]")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 6;
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LEVEL 0 FOR 80.0;
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LEVEL 1 FOR 80.0;
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}
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LEVEL 0 FOR 40.0;
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}
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}
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TRANSITION_LIST("indec[2]")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 12;
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LEVEL 0 FOR 40.0;
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LEVEL 1 FOR 40.0;
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}
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LEVEL 0 FOR 40.0;
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}
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}
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TRANSITION_LIST("indec[1]")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 25;
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LEVEL 0 FOR 20.0;
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LEVEL 1 FOR 20.0;
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}
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}
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}
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TRANSITION_LIST("indec[0]")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 50;
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LEVEL 0 FOR 10.0;
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LEVEL 1 FOR 10.0;
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}
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "indec";
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EXPAND_STATUS = EXPANDED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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CHILDREN = 1, 2, 3, 4;
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}
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DISPLAY_LINE
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{
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CHANNEL = "indec[3]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 1;
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PARENT = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "indec[2]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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TREE_LEVEL = 1;
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PARENT = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "indec[1]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 3;
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TREE_LEVEL = 1;
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PARENT = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "indec[0]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 4;
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TREE_LEVEL = 1;
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PARENT = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout";
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EXPAND_STATUS = EXPANDED;
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RADIX = Binary;
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TREE_INDEX = 5;
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TREE_LEVEL = 0;
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CHILDREN = 6, 7, 8, 9, 10, 11, 12;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[6]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 6;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[5]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 7;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[4]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 8;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[3]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 9;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[2]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 10;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[1]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 11;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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DISPLAY_LINE
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{
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CHANNEL = "codeout[0]";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 12;
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TREE_LEVEL = 1;
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PARENT = 5;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;
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@ -48,4 +48,10 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name VERILOG_FILE jyh_4490_1.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -0,0 +1,23 @@
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module jyh_4490_1(codeout,indec);
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input[3:0] indec;
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output[6:0] codeout;
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reg[6:0] codeout;
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always @ (indec)
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begin
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case (indec)
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4'd0: codeout=7'b1111110;
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4'd1: codeout=7'b0110000;
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4'd2: codeout=7'b1101101;
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4'd3: codeout=7'b1111001;
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4'd4: codeout=7'b0110011;
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4'd5: codeout=7'b1011011;
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4'd6: codeout=7'b1011111;
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4'd7: codeout=7'b1110000;
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4'd8: codeout=7'b1111111;
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4'd9: codeout=7'b1111011;
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default: codeout=7'bx;
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endcase
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end
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endmodule
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Reference in New Issue