虽然还不好用，但可以存一下

Quartus/v3/jyh_4490_3.qsf

@@ -39,7 +39,7 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE6E22C8
-set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_3_counter
+set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_3_entry
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:56:36  四月 04, 2022"
 set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
@@ -49,11 +49,35 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
-set_global_assignment -name VERILOG_FILE jyh_4490_3_counter.v
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_33 -to load
+set_location_assignment PIN_30 -to upd
+set_location_assignment PIN_31 -to en
+set_location_assignment PIN_24 -to clr
+set_location_assignment PIN_89 -to clk
+set_location_assignment PIN_43 -to in0[3]
+set_location_assignment PIN_44 -to in0[2]
+set_location_assignment PIN_42 -to in0[0]
+set_location_assignment PIN_39 -to in0[1]
+set_location_assignment PIN_54 -to out0[3]
+set_location_assignment PIN_46 -to out0[0]
+set_location_assignment PIN_50 -to out0[1]
+set_location_assignment PIN_52 -to out0[2]
+set_location_assignment PIN_49 -to out1[3]
+set_location_assignment PIN_51 -to out1[2]
+set_location_assignment PIN_53 -to out1[1]
+set_location_assignment PIN_58 -to out1[0]
+set_location_assignment PIN_142 -to in1[3]
+set_location_assignment PIN_10 -to in1[2]
+set_location_assignment PIN_11 -to in1[1]
+set_location_assignment PIN_7 -to in1[0]
+set_location_assignment PIN_144 -to CO
+set_global_assignment -name VERILOG_FILE jyh_4490_3_encoder.v
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_global_assignment -name VERILOG_FILE jyh_4490_3_counter.v
+set_global_assignment -name VERILOG_FILE jyh_4490_3_entry.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/v3/jyh_4490_3_counter.v

@@ -1,8 +1,9 @@
-module jyh_4490_3_counter(out,clk,clr,load,in,en,upd);
+module jyh_4490_3_counter(Q,clk,clr,load,in,en,upd,co);
 
 input[3:0] in;
 input en,clk,clr,load,upd;
-output reg [3:0] out;
+output reg [3:0] Q;
+output reg co;
 
 
 always@(posedge clk,negedge clr)
@@ -10,32 +11,47 @@ begin
 
 	//异步清零
 	if(!clr)
-		out<=0;
+		Q<=0;
 	
 	else if(en)
 	begin	
 		//同步置数
 		if(load)
-			out<=in;
+			begin
+			Q<=in;
+			co<=1'b1;
+			end
 			
 		//正反计数
 		else if(upd)
 			begin
-				if(out>=4'd9)
+				if(Q>=4'd9)
-					out=4'd0;
+					begin
-				else
+					Q<=4'd0;
-				out <= out+1;
+					co<=1'b1;
 					end
 				else
 					begin
-				if(out<=4'd0)
+					Q <= Q+1;
-					out=4'd9;
+					co<=0;
-				else
-				out <= out-1;
 					end
 			end
 		else 
-		out<=0;
+			begin
+				if(Q<=4'd0)
+					begin
+					Q<=4'd9;
+					co<=1'b1;
+					end
+				else
+					begin
+					Q <= Q-1;
+					co<=0;
+					end
+			end
+	end
+	else
+		Q<=0;
 end
 endmodule
 

Quartus/v3/jyh_4490_3_encoder.v

@@ -0,0 +1,57 @@
+module jyh_4490_3_encoder(codeout,indec,indec2,clk,seg);
+	input[3:0] indec,indec2;
+	input clk;
+	output reg [1:0] seg=2'b01;
+	output reg [6:0] codeout;
+	
+	reg n = 1;
+	
+always @ (posedge clk)
+ 	begin
+	if(n==1)
+	begin
+		n<=2;
+		if(seg==2'b01)
+		begin
+			case (indec)
+				4'd0: codeout<=7'b1111110;
+				4'd1: codeout<=7'b0110000;
+				4'd2: codeout<=7'b1101101;
+				4'd3: codeout<=7'b1111001;
+				4'd4: codeout<=7'b0110011;
+				4'd5: codeout<=7'b1011011;
+				4'd6: codeout<=7'b1011111;
+				4'd7: codeout<=7'b1110000;
+				4'd8: codeout<=7'b1111111;
+				4'd9: codeout<=7'b1111011;
+				default:		codeout<=7'bx;
+			endcase
+		end
+		if(seg==2'b10)
+		begin
+			case (indec2)
+				4'd0: codeout<=7'b1111110;
+				4'd1: codeout<=7'b0110000;
+				4'd2: codeout<=7'b1101101;
+				4'd3: codeout<=7'b1111001;
+				4'd4: codeout<=7'b0110011;
+				4'd5: codeout<=7'b1011011;
+				4'd6: codeout<=7'b1011111;
+				4'd7: codeout<=7'b1110000;
+				4'd8: codeout<=7'b1111111;
+				4'd9: codeout<=7'b1111011;
+				default:		codeout<=7'bx;
+			endcase
+		end
+	end
+	if(n==2)
+	begin
+		n<=1;
+		codeout<=7'b0;
+		if(seg==2'b10)
+			seg<=2'b01;
+		else if(seg==2'b10)
+			seg<=2'b01;
+	end
+end
+endmodule

Quartus/v3/jyh_4490_3_entry.v

@@ -0,0 +1,44 @@
+module jyh_4490_3_entry(out1,		out0,		code,		seg, 		CO,
+							//	十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
+								in1,		in0,		load,		clk,		clk2,			clr,			en,			upd);
+							// 十位装载 个位装载 	装载信号 	时钟信号 	数码管时钟		清零信号 		使能信号 		正反计数标志位
+
+output [3:0] out1;
+output [3:0] out0;
+output [6:0] code;
+output [1:0] seg;
+output CO;
+input [3:0] in1;
+input [3:0] in0;
+input clk,load,clr,en,upd,clk2;
+
+//个位计数器
+jyh_4490_3_counter c0(
+.Q(out0),
+.clk(clk),
+.co(CO),
+.clr(clr),
+.load(load),
+.in(in0),
+.en(en),
+.upd(upd));
+
+//十位计数器
+jyh_4490_3_counter c1(
+.Q(out1),
+.clk(CO),
+.clr(clr),
+.load(load),
+.in(in1),
+.en(en),
+.upd(upd));
+
+jyh_4490_3_encoder e1(
+.codeout(code),
+.indec(out0),
+.indec2(out1),
+.clk(clk2),
+.seg(seg)
+);
+
+endmodule