feat(数电课设): 搭框架
This commit is contained in:
iridiumR
parent
be4e36e240
commit
6116e09e28
14 changed files with 163 additions and 85 deletions
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@ -7,8 +7,7 @@
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<irq preferredWidth="34" />
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</columns>
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</systemtable>
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<library
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expandedCategories="Library/Interface Protocols/Ethernet/Reference Design Components,Library/University Program,Library/University Program/Clock,Library/Basic Functions/Simulation; Debug and Verification/Simulation,Library/Interface Protocols/Audio & Video,Library,Project,Library/Interface Protocols/Ethernet,Library/University Program/Audio & Video,Library/Basic Functions/Bridges and Adaptors/Clock,Library/Qsys Interconnect/Interrupt,Library/Basic Functions,Library/DSP,Library/University Program/Audio & Video/Video,Library/Basic Functions/Simulation; Debug and Verification,Library/Basic Functions/Bridges and Adaptors/Memory Mapped,Library/Basic Functions/Bridges and Adaptors,Library/Qsys Interconnect/Memory-Mapped Alpha,Library/Basic Functions/Clocks; PLLs and Resets,Library/Qsys Interconnect,Library/Interface Protocols,Library/Basic Functions/On Chip Memory,Library/DSP/Video and Image Processing" />
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<window width="1313" height="756" x="542" y="384" />
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||||
<library expandedCategories="Library,Project" />
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||||
<window width="1920" height="1034" x="0" y="0" />
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||||
<hdlexample language="VERILOG" />
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</preferences>
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@ -836,7 +836,7 @@
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<node nodeId="1386283918535" orientation="VERTICAL" divider="0.75">
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<node nodeId="1411773916307" orientation="HORIZONTAL" divider="0.3570504527813712">
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<node nodeId="1411773956584" orientation="VERTICAL" divider="0.5092667203867848">
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||||
<leaf id="3" nodeId="1411773916305">
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<leaf id="0" nodeId="1411773916305">
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<placeholders>
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<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
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<placeholder>dock.single.IP\ Catalog</placeholder>
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@ -939,7 +939,7 @@
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</placeholder-map>
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</leaf>
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</node>
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<leaf id="0" nodeId="1372710005745">
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<leaf id="3" nodeId="1372710005745">
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<placeholders>
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<placeholder>dock.single.Messages</placeholder>
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<placeholder>dock.single.Generation\ Messages</placeholder>
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@ -1005,10 +1005,10 @@
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</adjacent>
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<children ignore="false">
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<child>
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<layout factory="predefined" placeholder="dock.single.Messages">
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<replacement id="dockablesingle Messages"/>
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<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
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<replacement id="dockablesingle IP Catalog"/>
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<delegate id="delegate_ccontrol backup factory id">
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<id>Messages</id>
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<id>IP Catalog</id>
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<area/>
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</delegate>
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</layout>
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@ -1084,10 +1084,10 @@
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</children>
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</child>
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<child>
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<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
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<replacement id="dockablesingle IP Catalog"/>
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<layout factory="predefined" placeholder="dock.single.Messages">
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<replacement id="dockablesingle Messages"/>
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<delegate id="delegate_ccontrol backup factory id">
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<id>IP Catalog</id>
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<id>Messages</id>
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<area/>
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</delegate>
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</layout>
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@ -1095,7 +1095,7 @@
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</child>
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<child>
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<layout factory="delegate_StackDockStationFactory">
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<selected>1</selected>
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<selected>0</selected>
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<placeholders>
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<version>0</version>
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||||
<format>dock.PlaceholderList</format>
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||||
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@ -1348,12 +1348,9 @@
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<property factory="SplitDockPlaceholderProperty">
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<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
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<backup-path>
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<node location="RIGHT" size="0.25" id="1372710005727"/>
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||||
<node location="LEFT" size="0.6950092421441774" id="1375899667063"/>
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<node location="TOP" size="0.75" id="1386283918535"/>
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<node location="LEFT" size="0.3570504527813712" id="1411773916307"/>
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<node location="TOP" size="0.5092667203867848" id="1411773956584"/>
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<leaf id="1411773916305"/>
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<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
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<node location="TOP" size="0.504054054054054" id="1375985011088"/>
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<leaf id="1375985003630"/>
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</backup-path>
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</property>
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<property factory="StackDockPropertyFactory">
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@ -1859,15 +1856,13 @@
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<property factory="SplitDockPlaceholderProperty">
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<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
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<backup-path>
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<node location="RIGHT" size="0.25" id="1372710005727"/>
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||||
<node location="LEFT" size="0.6950092421441774" id="1375899667063"/>
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<node location="TOP" size="0.75" id="1386283918535"/>
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<node location="RIGHT" size="0.7106666666666666" id="1389811727550"/>
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<leaf id="1375899667061"/>
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<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
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<node location="TOP" size="0.504054054054054" id="1375985011088"/>
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<leaf id="1375985003630"/>
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</backup-path>
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</property>
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<property factory="StackDockPropertyFactory">
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<index>1</index>
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<index>2</index>
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<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
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</property>
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</location>
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@ -1,11 +1,14 @@
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst unsaved.rs232_0 -pg 1 -lvl 1 -y 30
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preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.clk,(SLAVE)rs232_0.clk) 1 0 1 NJ
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.interrupt,(SLAVE)rs232_0.interrupt) 1 0 1 NJ
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.reset,(SLAVE)rs232_0.reset) 1 0 1 NJ
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.avalon_rs232_slave,(SLAVE)rs232_0.avalon_rs232_slave) 1 0 1 NJ
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.external_interface,(SLAVE)rs232_0.external_interface) 1 0 1 NJ
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levelinfo -pg 1 0 120 320
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levelinfo -hier unsaved 130 160 310
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preplace inst uart_screen.clk_0 -pg 1 -lvl 1 -y 30
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preplace inst uart_screen.rs232_0 -pg 1 -lvl 2 -y 90
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preplace inst uart_screen -pg 1 -lvl 1 -y 40 -regy -20
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preplace netloc EXPORT<net_container>uart_screen</net_container>(SLAVE)uart_screen.rs232_0_avalon_data_transmit_sink,(SLAVE)rs232_0.avalon_data_transmit_sink) 1 0 2 NJ 100 NJ
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preplace netloc EXPORT<net_container>uart_screen</net_container>(SLAVE)uart_screen.clk,(SLAVE)clk_0.clk_in) 1 0 1 NJ
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preplace netloc EXPORT<net_container>uart_screen</net_container>(MASTER)rs232_0.avalon_data_receive_source,(MASTER)uart_screen.rs232_0_avalon_data_receive_source) 1 2 1 N
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preplace netloc EXPORT<net_container>uart_screen</net_container>(SLAVE)clk_0.clk_in_reset,(SLAVE)uart_screen.reset) 1 0 1 NJ
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preplace netloc POINT_TO_POINT<net_container>uart_screen</net_container>(SLAVE)rs232_0.reset,(MASTER)clk_0.clk_reset) 1 1 1 410
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preplace netloc POINT_TO_POINT<net_container>uart_screen</net_container>(SLAVE)rs232_0.clk,(MASTER)clk_0.clk) 1 1 1 430
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preplace netloc EXPORT<net_container>uart_screen</net_container>(SLAVE)rs232_0.external_interface,(SLAVE)uart_screen.rs232_0_external_interface) 1 0 2 NJ 140 NJ
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levelinfo -pg 1 0 200 900
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levelinfo -hier uart_screen 210 240 460 680
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@ -1,14 +1,91 @@
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module design(
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input wire clk,//50MHz时钟
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output reg led, //用于指示
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input wire rst_n,
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input wire rxd,
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output wire txd,
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inout dht_io
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);
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reg [31:0]cnt;
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reg led_f1,tx_flag;
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always@(posedge clk)
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begin
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led_f1 <= led;
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tx_flag <= led &(~led_f1);
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if(cnt >= 32'd25000000 - 1)
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begin
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cnt <= 0;
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led <=~led;
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end
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else begin
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cnt <= cnt + 1'b1 ;
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end
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end
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//--------------------------------------------
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localparam s_s1=0;
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localparam s_s2=1;
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localparam s_s3=2;
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localparam s_s4=3;
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reg [7:0]send_data;
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reg to_uart_valid , to_uart_ready;
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reg [2:0]send_st;
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reg [7:0]data_cnt;
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always@(posedge clk)
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begin
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if(!rst_n)begin
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to_uart_ready <= 1'b0;
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to_uart_valid <= 1'b0;
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send_data <= 8'd0;
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send_st<= s_s1;
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data_cnt <= 8'd0;
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end
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else begin
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case(send_st)
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s_s1:begin//待机
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if(tx_flag)begin
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send_st <= s_s2;
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to_uart_valid <= 1'b0;
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to_uart_ready<= 1'b0;
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data_cnt <= 8'd0;
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send_data <= 9;
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end
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else begin
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to_uart_valid <= 1'b0;
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to_uart_ready<= 1'b0;
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end
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end
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s_s2:begin
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if(data_cnt <= 8'd8-1'b1)begin
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to_uart_valid <= 1'b1;
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send_data <= data_cnt+1;
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data_cnt <= data_cnt + 1'b1;
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send_st <= (data_cnt >= 8'd5-1)?s_s3:s_s2;
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end
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end
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s_s3:begin
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to_uart_valid <= 1'b0;
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to_uart_ready <= 1'b1;
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send_st <= s_s1;
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data_cnt<=8'd0;
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end
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default :send_st <= s_s1;
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endcase
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end
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end
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uart_screen u0 (
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.clk_clk (<connected-to-clk_clk>), // clk.clk
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.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
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.rs232_0_from_uart_ready (<connected-to-rs232_0_from_uart_ready>), // rs232_0_avalon_data_receive_source.ready
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.rs232_0_from_uart_data (<connected-to-rs232_0_from_uart_data>), // .data
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.rs232_0_from_uart_error (<connected-to-rs232_0_from_uart_error>), // .error
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.rs232_0_from_uart_valid (<connected-to-rs232_0_from_uart_valid>), // .valid
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.rs232_0_to_uart_data (<connected-to-rs232_0_to_uart_data>), // rs232_0_avalon_data_transmit_sink.data
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.rs232_0_to_uart_error (<connected-to-rs232_0_to_uart_error>), // .error
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.rs232_0_to_uart_valid (<connected-to-rs232_0_to_uart_valid>), // .valid
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.rs232_0_to_uart_ready (<connected-to-rs232_0_to_uart_ready>), // .ready
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.rs232_0_UART_RXD (<connected-to-rs232_0_UART_RXD>), // rs232_0_external_interface.RXD
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.rs232_0_UART_TXD (<connected-to-rs232_0_UART_TXD>) // .TXD
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.rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data
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.rs232_0_to_uart_error (), // .error
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.rs232_0_to_uart_valid (to_uart_valid), // .valid
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.rs232_0_to_uart_ready (to_uart_ready), // .ready
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.rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD
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.rs232_0_UART_TXD (txd), // .TXD
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.clk_clk (clk), // clk.clk
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.reset_reset_n (rst_n) // reset.reset_n
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);
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endmodule
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@ -6,7 +6,7 @@
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="" />
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element clk_0
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@ -39,7 +39,7 @@
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="projectName" value="design.qpf" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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@ -93,7 +93,7 @@
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<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="avalon_bus_type" value="Streaming" />
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<parameter name="baud" value="115200" />
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<parameter name="baud" value="9600" />
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<parameter name="data_bits" value="8" />
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<parameter name="parity" value="None" />
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<parameter name="stop_bits" value="1" />
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="uart_screen" kind="uart_screen" version="1.0" fabric="QSYS">
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<!-- Format version 21.1 842 (Future versions may contain additional information.) -->
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<!-- 2022.05.24.19:49:50 -->
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<!-- 2022.06.14.11:25:23 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1653392990</value>
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<value>1655177123</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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@ -424,7 +424,7 @@ the requested settings for a module instance. -->
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</parameter>
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<parameter name="baud">
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<type>int</type>
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<value>115200</value>
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<value>9600</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
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@ -55,9 +55,9 @@ module uart_screen_rs232_0 (
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* Parameter Declarations *
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*****************************************************************************/
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parameter CW = 9; // Baud counter width
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parameter BAUD_TICK_COUNT = 434;
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parameter HALF_BAUD_TICK_COUNT = 217;
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parameter CW = 13; // Baud counter width
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parameter BAUD_TICK_COUNT = 5208;
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parameter HALF_BAUD_TICK_COUNT = 2604;
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parameter TDW = 10; // Total data width
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parameter DW = 8; // Data width
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@ -1,7 +1,7 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="uart_screen" kind="system" version="21.1" fabric="QSYS">
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<!-- Format version 21.1 842 (Future versions may contain additional information.) -->
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<!-- 2022.05.24.19:49:50 -->
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<!-- 2022.06.14.11:25:23 -->
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<!-- A collection of modules and connections -->
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<parameter name="clockCrossingAdapter">
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<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
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@ -53,7 +53,7 @@
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</parameter>
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<parameter name="generationId">
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<type>int</type>
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<value>1653392990</value>
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<value>1655177123</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
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@ -101,7 +101,7 @@
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</parameter>
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<parameter name="projectName">
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<type>java.lang.String</type>
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<value></value>
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<value>design.qpf</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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@ -482,7 +482,7 @@ the requested settings for a module instance. -->
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</parameter>
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<parameter name="baud">
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<type>int</type>
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<value>115200</value>
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<value>9600</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
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@ -1610,5 +1610,5 @@ parameters are a RESULT of the module parameters. -->
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<version>21.1</version>
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</plugin>
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<reportVersion>21.1 842</reportVersion>
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<uniqueIdentifier>CCD9AC02D57D00000180F5E6E111</uniqueIdentifier>
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<uniqueIdentifier>2C16DBA514B800000181603E9758</uniqueIdentifier>
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</EnsembleReport>
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@ -2,7 +2,7 @@ set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_VERSION "21.1"
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_ENV "Qsys"
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set_global_assignment -library "uart_screen" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../uart_screen.sopcinfo"]
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name SLD_INFO "QSYS_NAME uart_screen HAS_SOPCINFO 1 GENERATION_ID 1653392990"
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name SLD_INFO "QSYS_NAME uart_screen HAS_SOPCINFO 1 GENERATION_ID 1655177123"
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set_global_assignment -library "uart_screen" -name MISC_FILE [file join $::quartus(qip_path) "../uart_screen.cmp"]
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set_global_assignment -library "uart_screen" -name SLD_FILE [file join $::quartus(qip_path) "uart_screen.debuginfo"]
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
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@ -15,7 +15,7 @@ set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMP
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set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1MzM5Mjk5MA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1NTE3NzEyMw==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0U2RTIyQzg=::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
|
|
@ -62,7 +62,7 @@ set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name
|
|||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_VERSION "MTcuMQ=="
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_DESCRIPTION "UlMyMzIgVUFSVCBDb250cm9sbGVy"
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YXZhbG9uX2J1c190eXBl::U3RyZWFtaW5n::QXZhbG9uIFR5cGU="
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCBSYXRlIChicHMp"
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YmF1ZA==::OTYwMA==::QmF1ZCBSYXRlIChicHMp"
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tm9uZQ==::UGFyaXR5"
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "ZGF0YV9iaXRz::OA==::RGF0YSBCaXRz"
|
||||
set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "c3RvcF9iaXRz::MQ==::U3RvcCBCaXRz"
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2022.05.24.19:49:50</td>
|
||||
<td class="l">2022.06.14.11:25:23</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
|
@ -185,7 +185,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">baud</td>
|
||||
<td class="parametervalue">115200</td>
|
||||
<td class="parametervalue">9600</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">parity</td>
|
||||
|
|
@ -229,7 +229,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
|
|||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0.00 seconds</td>
|
||||
<td class="r">rendering took 0.03 seconds</td>
|
||||
<td class="r">rendering took 0.01 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2022.05.24.19:49:50"
|
||||
date="2022.06.14.11:25:23"
|
||||
outputDirectory="/home/ir/Documents/codelib/Quartus/Design/uart_screen/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
|
|
@ -133,13 +133,13 @@
|
|||
</perimeter>
|
||||
<entity
|
||||
path=""
|
||||
parameterizationKey="uart_screen:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE6E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1653392990,AUTO_UNIQUE_ID=(clock_source:21.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=5.0E7,stop_bits=1)(clock:21.1:)(reset:21.1:)"
|
||||
parameterizationKey="uart_screen:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE6E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1655177123,AUTO_UNIQUE_ID=(clock_source:21.1:clockFrequency=50000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=9600,data_bits=8,parity=None,ref_clk_freq=5.0E7,stop_bits=1)(clock:21.1:)(reset:21.1:)"
|
||||
instancePathKey="uart_screen"
|
||||
kind="uart_screen"
|
||||
version="1.0"
|
||||
name="uart_screen">
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="1653392990" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="1655177123" />
|
||||
<parameter name="AUTO_DEVICE" value="EP4CE6E22C8" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
|
||||
<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
|
||||
|
|
@ -226,12 +226,12 @@
|
|||
</entity>
|
||||
<entity
|
||||
path="submodules/"
|
||||
parameterizationKey="altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=5.0E7,stop_bits=1"
|
||||
parameterizationKey="altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=50000000,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=9600,data_bits=8,parity=None,ref_clk_freq=5.0E7,stop_bits=1"
|
||||
instancePathKey="uart_screen:.:rs232_0"
|
||||
kind="altera_up_avalon_rs232"
|
||||
version="17.1"
|
||||
name="uart_screen_rs232_0">
|
||||
<parameter name="baud" value="115200" />
|
||||
<parameter name="baud" value="9600" />
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="stop_bits" value="1" />
|
||||
<parameter name="ref_clk_freq" value="5.0E7" />
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
module uart_screen (
|
||||
rs232_0_UART_RXD,
|
||||
rs232_0_UART_TXD,
|
||||
clk_clk,
|
||||
reset_reset_n,
|
||||
rs232_0_from_uart_ready,
|
||||
rs232_0_from_uart_data,
|
||||
rs232_0_from_uart_error,
|
||||
|
|
@ -10,11 +10,11 @@ module uart_screen (
|
|||
rs232_0_to_uart_error,
|
||||
rs232_0_to_uart_valid,
|
||||
rs232_0_to_uart_ready,
|
||||
clk_clk,
|
||||
reset_reset_n);
|
||||
rs232_0_UART_RXD,
|
||||
rs232_0_UART_TXD);
|
||||
|
||||
input rs232_0_UART_RXD;
|
||||
output rs232_0_UART_TXD;
|
||||
input clk_clk;
|
||||
input reset_reset_n;
|
||||
input rs232_0_from_uart_ready;
|
||||
output [7:0] rs232_0_from_uart_data;
|
||||
output rs232_0_from_uart_error;
|
||||
|
|
@ -23,6 +23,6 @@ module uart_screen (
|
|||
input rs232_0_to_uart_error;
|
||||
input rs232_0_to_uart_valid;
|
||||
output rs232_0_to_uart_ready;
|
||||
input clk_clk;
|
||||
input reset_reset_n;
|
||||
input rs232_0_UART_RXD;
|
||||
output rs232_0_UART_TXD;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@ Info: Starting: Create block symbol file (.bsf)
|
|||
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8
|
||||
Progress: Loading Design/uart_screen.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding clk_0 [clock_source 21.1]
|
||||
Progress: Parameterizing module clk_0
|
||||
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
|
||||
Progress: Parameterizing module rs232_0
|
||||
Progress: Building connections
|
||||
|
|
@ -15,6 +17,8 @@ Info: Starting: Create HDL design files for synthesis
|
|||
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
|
||||
Progress: Loading Design/uart_screen.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding clk_0 [clock_source 21.1]
|
||||
Progress: Parameterizing module clk_0
|
||||
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
|
||||
Progress: Parameterizing module rs232_0
|
||||
Progress: Building connections
|
||||
|
|
@ -23,8 +27,8 @@ Progress: Validating
|
|||
Progress: Done reading input file
|
||||
Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH
|
||||
Info: rs232_0: Starting Generation of RS232 UART
|
||||
Error: rs232_0: The input clock frequency must be known at generation time.
|
||||
Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0"
|
||||
Info: uart_screen: Done "uart_screen" with 2 modules, 6 files
|
||||
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
|
||||
Info: rst_controller: "uart_screen" instantiated altera_reset_controller "rst_controller"
|
||||
Info: uart_screen: Done "uart_screen" with 3 modules, 9 files
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
uart_screen u0 (
|
||||
.rs232_0_UART_RXD (<connected-to-rs232_0_UART_RXD>), // rs232_0_external_interface.RXD
|
||||
.rs232_0_UART_TXD (<connected-to-rs232_0_UART_TXD>), // .TXD
|
||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
||||
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
|
||||
.rs232_0_from_uart_ready (<connected-to-rs232_0_from_uart_ready>), // rs232_0_avalon_data_receive_source.ready
|
||||
.rs232_0_from_uart_data (<connected-to-rs232_0_from_uart_data>), // .data
|
||||
.rs232_0_from_uart_error (<connected-to-rs232_0_from_uart_error>), // .error
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
.rs232_0_to_uart_error (<connected-to-rs232_0_to_uart_error>), // .error
|
||||
.rs232_0_to_uart_valid (<connected-to-rs232_0_to_uart_valid>), // .valid
|
||||
.rs232_0_to_uart_ready (<connected-to-rs232_0_to_uart_ready>), // .ready
|
||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
||||
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
|
||||
.rs232_0_UART_RXD (<connected-to-rs232_0_UART_RXD>), // rs232_0_external_interface.RXD
|
||||
.rs232_0_UART_TXD (<connected-to-rs232_0_UART_TXD>) // .TXD
|
||||
);
|
||||
|
||||
|
|
|
|||
Reference in a new issue