数电实验3
This commit is contained in:
iridiumR
parent
b08836068f
commit
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4 changed files with 639 additions and 0 deletions
508
Quartus/v3/Waveform.vwf
Normal file
508
Quartus/v3/Waveform.vwf
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@ -0,0 +1,508 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_3 -c jyh_4490_3 --vector_source="/home/ir/Documents/codelib/Quartus/v3/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_3 -c jyh_4490_3 --vector_source="/home/ir/Documents/codelib/Quartus/v3/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/" jyh_4490_3 -c jyh_4490_3</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v3/simulation/qsim/" jyh_4490_3 -c jyh_4490_3</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_3.vo
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vlog -work work Waveform.vwf.vt
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vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_counter_vlg_vec_tst
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vcd file -direction jyh_4490_3.msim.vcd
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vcd add -internal jyh_4490_3_counter_vlg_vec_tst/*
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vcd add -internal jyh_4490_3_counter_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_3.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_counter_vlg_vec_tst
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vcd file -direction jyh_4490_3.msim.vcd
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vcd add -internal jyh_4490_3_counter_vlg_vec_tst/*
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vcd add -internal jyh_4490_3_counter_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("clk")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("clr")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("en")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("in")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 4;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("in[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in";
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}
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SIGNAL("in[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in";
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}
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SIGNAL("in[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in";
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}
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SIGNAL("in[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "in";
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}
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SIGNAL("load")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("out")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 4;
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LSB_INDEX = 0;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("out[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "out";
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}
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SIGNAL("out[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "out";
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}
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SIGNAL("out[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "out";
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}
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SIGNAL("out[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "out";
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}
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SIGNAL("upd")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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TRANSITION_LIST("clk")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 33;
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LEVEL 0 FOR 15.0;
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LEVEL 1 FOR 15.0;
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}
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LEVEL 0 FOR 10.0;
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}
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}
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TRANSITION_LIST("clr")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 590.0;
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LEVEL 0 FOR 60.0;
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LEVEL 1 FOR 350.0;
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}
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}
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TRANSITION_LIST("en")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 30.0;
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LEVEL 1 FOR 970.0;
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}
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}
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TRANSITION_LIST("in[3]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 1000.0;
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}
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}
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TRANSITION_LIST("in[2]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 1 FOR 1000.0;
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}
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}
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TRANSITION_LIST("in[1]")
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{
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NODE
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{
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|
REPEAT = 1;
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|
LEVEL 1 FOR 1000.0;
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|
}
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|
}
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TRANSITION_LIST("in[0]")
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|
{
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|
NODE
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|
{
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REPEAT = 1;
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|
LEVEL 0 FOR 1000.0;
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|
}
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|
}
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|
TRANSITION_LIST("load")
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|
{
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|
NODE
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|
{
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|
REPEAT = 1;
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|
LEVEL 0 FOR 680.0;
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|
LEVEL 1 FOR 30.0;
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|
LEVEL 0 FOR 290.0;
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|
}
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|
}
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TRANSITION_LIST("out[3]")
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|
{
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|
NODE
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|
{
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|
REPEAT = 1;
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|
LEVEL X FOR 1000.0;
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|
}
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|
}
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|
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|
TRANSITION_LIST("out[2]")
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|
{
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|
NODE
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|
{
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|
REPEAT = 1;
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|
LEVEL X FOR 1000.0;
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|
}
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|
}
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|
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TRANSITION_LIST("out[1]")
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|
{
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|
NODE
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|
{
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|
REPEAT = 1;
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|
LEVEL X FOR 1000.0;
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|
}
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|
}
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|
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|
TRANSITION_LIST("out[0]")
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|
{
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|
NODE
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|
{
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|
REPEAT = 1;
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|
LEVEL X FOR 1000.0;
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|
}
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|
}
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|
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|
TRANSITION_LIST("upd")
|
||||||
|
{
|
||||||
|
NODE
|
||||||
|
{
|
||||||
|
REPEAT = 1;
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||||||
|
LEVEL 0 FOR 400.0;
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|
LEVEL 1 FOR 600.0;
|
||||||
|
}
|
||||||
|
}
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|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "clk";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Binary;
|
||||||
|
TREE_INDEX = 0;
|
||||||
|
TREE_LEVEL = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "upd";
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||||||
|
EXPAND_STATUS = COLLAPSED;
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||||||
|
RADIX = Binary;
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|
TREE_INDEX = 1;
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|
TREE_LEVEL = 0;
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|
}
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|
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DISPLAY_LINE
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{
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CHANNEL = "clr";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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|
TREE_LEVEL = 0;
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|
}
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|
|
||||||
|
DISPLAY_LINE
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|
{
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|
CHANNEL = "en";
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|
EXPAND_STATUS = COLLAPSED;
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||||||
|
RADIX = Binary;
|
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|
TREE_INDEX = 3;
|
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|
TREE_LEVEL = 0;
|
||||||
|
}
|
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|
|
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|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "out";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
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||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 4;
|
||||||
|
TREE_LEVEL = 0;
|
||||||
|
CHILDREN = 5, 6, 7, 8;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "out[3]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 5;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "out[2]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 6;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "out[1]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 7;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "out[0]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 8;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "load";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Binary;
|
||||||
|
TREE_INDEX = 9;
|
||||||
|
TREE_LEVEL = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "in";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 10;
|
||||||
|
TREE_LEVEL = 0;
|
||||||
|
CHILDREN = 11, 12, 13, 14;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "in[3]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 11;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 10;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "in[2]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 12;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 10;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "in[1]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 13;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 10;
|
||||||
|
}
|
||||||
|
|
||||||
|
DISPLAY_LINE
|
||||||
|
{
|
||||||
|
CHANNEL = "in[0]";
|
||||||
|
EXPAND_STATUS = COLLAPSED;
|
||||||
|
RADIX = Unsigned;
|
||||||
|
TREE_INDEX = 14;
|
||||||
|
TREE_LEVEL = 1;
|
||||||
|
PARENT = 10;
|
||||||
|
}
|
||||||
|
|
||||||
|
TIME_BAR
|
||||||
|
{
|
||||||
|
TIME = 0;
|
||||||
|
MASTER = TRUE;
|
||||||
|
}
|
||||||
|
;
|
||||||
31
Quartus/v3/jyh_4490_3.qpf
Normal file
31
Quartus/v3/jyh_4490_3.qpf
Normal file
|
|
@ -0,0 +1,31 @@
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus Prime
|
||||||
|
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||||
|
# Date created = 17:56:36 四月 04, 2022
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
QUARTUS_VERSION = "21.1"
|
||||||
|
DATE = "17:56:36 四月 04, 2022"
|
||||||
|
|
||||||
|
# Revisions
|
||||||
|
|
||||||
|
PROJECT_REVISION = "jyh_4490_3"
|
||||||
59
Quartus/v3/jyh_4490_3.qsf
Normal file
59
Quartus/v3/jyh_4490_3.qsf
Normal file
|
|
@ -0,0 +1,59 @@
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||||
|
# Your use of Intel Corporation's design tools, logic functions
|
||||||
|
# and other software and tools, and any partner logic
|
||||||
|
# functions, and any output files from any of the foregoing
|
||||||
|
# (including device programming or simulation files), and any
|
||||||
|
# associated documentation or information are expressly subject
|
||||||
|
# to the terms and conditions of the Intel Program License
|
||||||
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
# agreement, including, without limitation, that your use is for
|
||||||
|
# the sole purpose of programming logic devices manufactured by
|
||||||
|
# Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
# refer to the applicable agreement for further details, at
|
||||||
|
# https://fpgasoftware.intel.com/eula.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Quartus Prime
|
||||||
|
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||||
|
# Date created = 17:56:36 四月 04, 2022
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
#
|
||||||
|
# Notes:
|
||||||
|
#
|
||||||
|
# 1) The default values for assignments are stored in the file:
|
||||||
|
# jyh_4490_3_assignment_defaults.qdf
|
||||||
|
# If this file doesn't exist, see file:
|
||||||
|
# assignment_defaults.qdf
|
||||||
|
#
|
||||||
|
# 2) Intel recommends that you do not modify this file. This
|
||||||
|
# file is updated automatically by the Quartus Prime software
|
||||||
|
# and any changes you make may be lost or overwritten.
|
||||||
|
#
|
||||||
|
# -------------------------------------------------------------------------- #
|
||||||
|
|
||||||
|
|
||||||
|
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||||
|
set_global_assignment -name DEVICE EP4CE6E22C8
|
||||||
|
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_3_counter
|
||||||
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
|
||||||
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:56:36 四月 04, 2022"
|
||||||
|
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
|
||||||
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||||
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||||
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||||
|
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||||
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||||
|
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||||
|
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||||
|
set_global_assignment -name VERILOG_FILE jyh_4490_3_counter.v
|
||||||
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||||
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||||
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||||
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||||
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||||
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||||
41
Quartus/v3/jyh_4490_3_counter.v
Normal file
41
Quartus/v3/jyh_4490_3_counter.v
Normal file
|
|
@ -0,0 +1,41 @@
|
||||||
|
module jyh_4490_3_counter(out,clk,clr,load,in,en,upd);
|
||||||
|
|
||||||
|
input[3:0] in;
|
||||||
|
input en,clk,clr,load,upd;
|
||||||
|
output reg [3:0] out;
|
||||||
|
|
||||||
|
|
||||||
|
always@(posedge clk,negedge clr)
|
||||||
|
begin
|
||||||
|
|
||||||
|
//异步清零
|
||||||
|
if(!clr)
|
||||||
|
out<=0;
|
||||||
|
|
||||||
|
else if(en)
|
||||||
|
begin
|
||||||
|
//同步置数
|
||||||
|
if(load)
|
||||||
|
out<=in;
|
||||||
|
|
||||||
|
//正反计数
|
||||||
|
else if(upd)
|
||||||
|
begin
|
||||||
|
if(out>=4'd9)
|
||||||
|
out=4'd0;
|
||||||
|
else
|
||||||
|
out <= out+1;
|
||||||
|
end
|
||||||
|
else
|
||||||
|
begin
|
||||||
|
if(out<=4'd0)
|
||||||
|
out=4'd9;
|
||||||
|
else
|
||||||
|
out <= out-1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else
|
||||||
|
out<=0;
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
||||||
Reference in a new issue