有点问题

Quartus/v4/jyh_4490_4_divider.v

@@ -1,7 +1,7 @@
 module jyh_4490_4_divider(clk,clk_out);
 	 input clk;
 	 output reg clk_out;
-    localparam TARGET=50000;
+    localparam TARGET=5;
 //	localparam TARGET=1;
     reg [19:0]counter=0; 
     initial begin

Quartus/v6/jyh_4490_6.qsf

@@ -39,7 +39,7 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE6E22C8
-set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_mstate
+set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_6_entry
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:39:46  五月 09, 2022"
 set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
@@ -50,7 +50,12 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
 set_global_assignment -name VERILOG_FILE jyh_4490_mstate.v
 set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench.v
+set_global_assignment -name VERILOG_FILE jyh_4490_6_counter.v
+set_global_assignment -name VERILOG_FILE jyh_4490_6_encoder.v
+set_global_assignment -name VERILOG_FILE jyh_4490_6_entry.v
+set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench_top.v
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VERILOG_FILE jyh_4490_6_divider.v

Quartus/v6/jyh_4490_6_counter.v

@@ -0,0 +1,69 @@
+module jyh_4490_6_counter(Q,clk,clr,load,in,en,upd,co);
+
+input[3:0] in;
+input en,clk,clr,load,upd;
+output reg [3:0] Q;
+output reg co;
+
+reg co_flag;
+
+always@(posedge clk,negedge clr)
+begin
+
+	//异步清零
+	if(!clr)
+		Q<=0;
+	
+	else if(en)
+	begin	
+		//同步置数
+		if(load)
+			begin
+			Q<=in;
+			co<=0;
+			end
+		else
+		begin
+			if(co_flag)
+			begin
+				co<=1;
+				co_flag=0;
+			end
+			else if(!co_flag)
+				co<=0;
+			//正反计数
+			 if(upd)
+				begin
+					if(Q>=4'd9)
+						begin
+						Q<=4'd0;
+						co_flag=1;
+						end
+					else
+						begin
+						Q <= Q+1;
+						end
+				end
+			else 
+				begin
+					if(Q<=4'd0)
+						begin
+						Q<=4'd9;
+						end
+					else if(Q==4'd1)
+						begin
+						Q <= Q-1;
+						co_flag=1;
+						end
+					else
+						begin
+						Q <= Q-1;
+						end
+				end
+			end
+	end
+	else
+		Q<=0;
+end
+endmodule
+

Quartus/v6/jyh_4490_6_divider.v

@@ -0,0 +1,19 @@
+module jyh_4490_6_divider(clk,clk_out);
+	 input clk;
+	 output reg clk_out;
+    localparam TARGET=50000;
+//	localparam TARGET=1;
+    reg [19:0]counter=0; 
+    initial begin
+        clk_out=0;
+    end
+    always @(posedge clk)
+	 begin
+        counter=counter+1;
+        if(counter==TARGET)
+			begin
+            counter=0;
+            clk_out=!clk_out;
+        end
+    end
+endmodule

Quartus/v6/jyh_4490_6_encoder.v

@@ -0,0 +1,70 @@
+//七段四位译码器
+module jyh_4490_4_encoder(sel,codeout,clk, d1, d2, d3, d4);
+input clk;
+input [6:0] d1, d2, d3, d4;
+output reg [3:0] sel; //位选
+output reg [6:0] codeout; //型码
+
+
+//当前位置数字
+reg [6:0] code_loc;
+
+//实验性消影
+reg isEnable;
+reg [3:0] loc=4'b1000;
+
+//循环移位
+always @(posedge clk)
+begin
+	if(isEnable)
+		isEnable<=0;
+	else
+		begin
+		isEnable<=1;
+		if(loc==4'b0001)
+		loc=4'b10;
+		else if(loc==4'b0010)
+		loc=4'b100;
+		else if(loc==4'b0100)
+		loc=4'b1000;
+		else if(loc==4'b1000)
+		loc=4'b1;
+		end
+end
+
+always @(*)
+begin
+	if(isEnable)
+	begin
+	case (loc)
+		4'b0001: begin code_loc = d1; sel = 4'b0001; end
+		4'b0010: begin code_loc = d2; sel = 4'b0010; end
+		4'b0100: begin code_loc = d3; sel = 4'b0100; end
+		4'b1000: begin code_loc = d4; sel = 4'b1000; end
+	endcase
+	end
+end
+	
+always @(*)
+begin
+	if(isEnable)
+	begin
+	case (code_loc)
+		4'd0: codeout<=7'b1111110;
+		4'd1: codeout<=7'b0110000;
+		4'd2: codeout<=7'b1101101;
+		4'd3: codeout<=7'b1111001;
+		4'd4: codeout<=7'b0110011;
+		4'd5: codeout<=7'b1011011;
+		4'd6: codeout<=7'b1011111;
+		4'd7: codeout<=7'b1110000;
+		4'd8: codeout<=7'b1111111;
+		4'd9: codeout<=7'b1111011;
+		default:		codeout<=7'bx;
+	endcase
+	end
+	else
+		codeout=7'b0;
+end
+
+endmodule

Quartus/v6/jyh_4490_6_entry.v

@@ -0,0 +1,61 @@
+module jyh_4490_6_entry(code,			seg,			clk_50m,		clr,		en,		in,
+							//数码管型码 		数码管位码    50M			清零信号 	使能信号	按键
+								out0,			out1,			subclk);
+							//计数值 							消抖值
+
+output [6:0] code;
+output [7:0] seg;
+input  clr,en,clk_50m,in;
+output subclk;
+output [3:0] out0;
+output [3:0] out1;
+
+wire CO;
+wire freshclk;
+
+reg upd;
+
+initial begin
+upd=1;
+end
+
+//分频器
+jyh_4490_6_divider D1(
+.clk(clk_50m),
+.clk_out(freshclk)
+);
+
+//个位计数器
+jyh_4490_6_counter C1(
+.Q(out0),
+.clk(subclk),
+.co(CO),
+.clr(clr),
+.en(en),
+.upd(upd));
+
+//十位计数器
+jyh_4490_6_counter C2(
+.Q(out1),
+.clk(CO||(subclk)),
+.clr(clr),
+.en(en),
+.upd(upd));
+
+//四位数码管译码器
+jyh_4490_4_encoder E1(
+.codeout(code),
+.d1(out0),
+.d2(out1),
+.clk(freshclk),
+.sel(seg[3:0])
+);
+
+//消抖模块
+jyh_4490_mstate M1(
+.clk(clk_50m),
+.in(in),
+.en(en),
+.out(subclk)
+);
+endmodule

Quartus/v6/jyh_4490_6_testbench.v

@@ -13,11 +13,12 @@ initial begin
 end
 
 always#10 clk=~clk;
-always#20000000
+always
 begin
 	in=0;
 	repeat(5)
 	begin
+		#10000000;
 		in=1;
 		#1000000;
 		in=0;
@@ -33,6 +34,7 @@ begin
 		#1000000;
 	end
 	in=0;
+	#10000000;
 end
 	
 jyh_4490_mstate M1(

Quartus/v6/jyh_4490_6_testbench_top.v

@@ -0,0 +1,50 @@
+`timescale 1ns/1ns
+module jyh_4490_6_testbench_top;
+reg clk;
+wire [6:0] code;
+wire [7:0] seg;
+wire [19:0] cnt;
+reg clr;
+reg in;
+reg en;
+wire subclk;
+wire [3:0] out0;
+wire [3:0] out1;
+
+initial begin
+	clk=0;
+	in=0;
+	clr=1;
+	en=1;
+end
+
+always#10 clk=~clk;
+always
+begin
+	in=0;
+	#15000000;
+	repeat(5)
+	begin
+		in=1;
+		#1000000;
+		in=0;
+		#1000000;
+	end
+	in=1;
+	#30000000;
+	repeat(5)
+	begin
+		in=0;
+		#1000000;
+		in=1;
+		#1000000;
+	end
+	in=0;
+	#15000000;
+end
+	
+jyh_4490_6_entry E1(.code(code),.seg(seg),.clk_50m(clk),.clr(clr),.en(en),.in(in),
+							//数码管型码 		数码管位码    50M				清零信号 	  使能信号	 按键
+								.out0(out0),.out1(out1),.subclk(subclk));
+							//计数值 							消抖值
+endmodule

Quartus/v6_testbench_top/jyh_4490_top.cr.mti

@@ -0,0 +1,43 @@
+/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_6_divider
+
+Top level modules:
+	jyh_4490_6_divider
+
+} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_4_encoder
+
+Top level modules:
+	jyh_4490_4_encoder
+
+} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_6_counter
+
+Top level modules:
+	jyh_4490_6_counter
+
+} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_mstate
+
+Top level modules:
+	jyh_4490_mstate
+
+} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_6_entry
+
+Top level modules:
+	jyh_4490_6_entry
+
+} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v
+Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
+-- Compiling module jyh_4490_6_testbench_top
+
+Top level modules:
+	jyh_4490_6_testbench_top
+
+} {} {}}

Quartus/v6_testbench_top/jyh_4490_top.mpf

@@ -0,0 +1,477 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+twentynm = $MODEL_TECH/../altera/vhdl/twentynm
+twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
+twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
+cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
+twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
+twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
+cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+suppress = 3116
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+[Project]
+** Warning: ; Warning -- Do not edit the project properties directly.
+;            Property names are dynamic in nature and property
+;            values have special syntax.  Changing property data directly
+;            can result in a corrupt MPF file.  All project properties
+;            can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 6
+Project_File_0 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v
+Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652174341 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v
+Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652171577 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v
+Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652170623 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
+Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652112350 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v
+Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652174396 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v
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+PCF_CustomDoubleClick = 
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Quartus/v6_testbench_top/transcript

@@ -0,0 +1,41 @@
+# Compile of jyh_4490_6_testbench_top.v was successful.
+vsim work.jyh_4490_6_testbench_top
+# vsim work.jyh_4490_6_testbench_top 
+# Start time: 17:29:53 on May 10,2022
+# Loading work.jyh_4490_6_testbench_top
+# Loading work.jyh_4490_6_entry
+# Loading work.jyh_4490_6_divider
+# Loading work.jyh_4490_6_counter
+# Loading work.jyh_4490_4_encoder
+# Loading work.jyh_4490_mstate
+# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'C1'.  Expected 8, found 6.
+#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/C1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 29
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(29): [TFMPC] - Missing connection for port 'load'.
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(29): [TFMPC] - Missing connection for port 'in'.
+# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'C2'.  Expected 8, found 5.
+#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/C2 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 38
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(38): [TFMPC] - Missing connection for port 'load'.
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(38): [TFMPC] - Missing connection for port 'in'.
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(38): [TFMPC] - Missing connection for port 'co'.
+# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'E1'.  Expected 7, found 5.
+#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 46
+# ** Warning: (vsim-3015) [PCDPC] - Port size (7) does not match connection size (4) for port 'd1'. The port definition is at: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v(2).
+#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 46
+# ** Warning: (vsim-3015) [PCDPC] - Port size (7) does not match connection size (4) for port 'd2'. The port definition is at: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v(2).
+#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 46
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(46): [TFMPC] - Missing connection for port 'd3'.
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(46): [TFMPC] - Missing connection for port 'd4'.
+# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'.  Expected 5, found 4.
+#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 55
+# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(55): [TFMPC] - Missing connection for port 'cnt'.
+add wave -position end  sim:/jyh_4490_6_testbench_top/clk
+add wave -position end  sim:/jyh_4490_6_testbench_top/code
+add wave -position end  sim:/jyh_4490_6_testbench_top/seg
+add wave -position end  sim:/jyh_4490_6_testbench_top/cnt
+add wave -position end  sim:/jyh_4490_6_testbench_top/clr
+add wave -position end  sim:/jyh_4490_6_testbench_top/in
+add wave -position end  sim:/jyh_4490_6_testbench_top/en
+add wave -position end  sim:/jyh_4490_6_testbench_top/subclk
+add wave -position end  sim:/jyh_4490_6_testbench_top/out0
+add wave -position end  sim:/jyh_4490_6_testbench_top/out1
+run -all

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+8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
+F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
+!i122 15
+L0 1 53
+R4
+r1
+!s85 0
+31
+R5
+!s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v|
+!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v|
+!i113 1
+R6
+R7

Quartus/v6_testbench_top/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

SoftwareDesign/Lab3/Lab3-2-2/Lab3-2-2.pro

@@ -16,7 +16,8 @@ DEFINES += QT_DEPRECATED_WARNINGS
 # In order to do so, uncomment the following line.
 # You can also select to disable deprecated APIs only up to a certain version of Qt.
 #DEFINES += QT_DISABLE_DEPRECATED_BEFORE=0x060000    # disables all the APIs deprecated before Qt 6.0.0
-
+DEFINES -= QT_NO_DEBUG_OUTPUT
+CONFIG += console
 
 SOURCES += \
         main.cpp \

SoftwareDesign/Lab3/Lab3-2-2/main.cpp

@@ -1,8 +1,11 @@
 #include "widget.h"
 #include <QApplication>
+#include <QLoggingCategory>
+#include <QtDebug>
 
 int main(int argc, char *argv[]) {
   QApplication a(argc, argv);
+  QLoggingCategory::defaultCategory()->setEnabled(QtDebugMsg, true);
   Widget w;
   w.show();
   return a.exec();

SoftwareDesign/Lab3/Lab3-2-2/widget.cpp

@@ -11,8 +11,6 @@
 
 Widget::Widget(QWidget *parent) : QWidget(parent), ui(new Ui::Widget) {
   ui->setupUi(this);
-
-  errorDlg = new QErrorMessage(this);
 }
 
 Widget::~Widget() { delete ui; }