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不知道有没有用的数码管消影

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iridiumR 2022-04-05 17:27:13 +08:00
parent 453edfb17a
commit 65009ea748
2 changed files with 24 additions and 9 deletions
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8
Quartus/v3/Waveform.vwf
View file

@ -26,6 +26,7 @@ quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
@ -50,6 +51,7 @@ quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
@ -684,9 +686,9 @@ TRANSITION_LIST("clk2")
REPEAT = 1;
NODE
{
REPEAT = 100;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
REPEAT = 200;
LEVEL 0 FOR 2.5;
LEVEL 1 FOR 2.5;
}
}
}

25
Quartus/v3/jyh_4490_3_encoder.v
View file

@ -7,30 +7,40 @@ output reg [6:0] codeout; //型码
//当前位置数字
reg [6:0] code_loc=2'B01;
reg [6:0] code_loc=2'b01;
reg isEnable;
reg [1:0] loc;
//循环移位
always @(posedge clk)
begin
if(loc==2'b01)
loc=2'b10;
if(isEnable)
isEnable<=0;
else
loc=2'b01;
begin
isEnable<=1;
if(loc==2'b01)
loc=2'b10;
else
loc=2'b01;
end
end
always @(*)
begin
sel = 4'b0000;
if(isEnable)
begin
case (loc)
2'b01: begin code_loc = d1; sel = 4'b10; end
2'b10: begin code_loc = d2; sel = 4'b01; end
endcase
end
end
always @(*)
begin
if(isEnable)
begin
case (code_loc)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
@ -44,6 +54,9 @@ begin
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
else
codeout=7'b0;
end
endmodule