小改BUG

Quartus/v4/jyh_4490_4.qsf

@@ -57,4 +57,38 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v
 set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_location_assignment PIN_43 -to CO
+set_location_assignment PIN_89 -to clk
+set_location_assignment PIN_24 -to clr
+set_location_assignment PIN_103 -to code[0]
+set_location_assignment PIN_110 -to code[1]
+set_location_assignment PIN_106 -to code[2]
+set_location_assignment PIN_111 -to code[3]
+set_location_assignment PIN_104 -to code[4]
+set_location_assignment PIN_100 -to code[5]
+set_location_assignment PIN_112 -to code[6]
+set_location_assignment PIN_31 -to en
+set_location_assignment PIN_32 -to in0[0]
+set_location_assignment PIN_42 -to in0[1]
+set_location_assignment PIN_39 -to in0[2]
+set_location_assignment PIN_44 -to in0[3]
+set_location_assignment PIN_33 -to load
+set_location_assignment PIN_46 -to out0[0]
+set_location_assignment PIN_50 -to out0[1]
+set_location_assignment PIN_52 -to out0[2]
+set_location_assignment PIN_54 -to out0[3]
+set_location_assignment PIN_58 -to out1[0]
+set_location_assignment PIN_53 -to out1[1]
+set_location_assignment PIN_51 -to out1[2]
+set_location_assignment PIN_49 -to out1[3]
+set_location_assignment PIN_119 -to seg[0]
+set_location_assignment PIN_126 -to seg[1]
+set_location_assignment PIN_115 -to seg[2]
+set_location_assignment PIN_125 -to seg[3]
+set_location_assignment PIN_114 -to seg[4]
+set_location_assignment PIN_121 -to seg[5]
+set_location_assignment PIN_113 -to seg[6]
+set_location_assignment PIN_120 -to seg[7]
+set_location_assignment PIN_30 -to upd
+set_location_assignment PIN_90 -to clk_50m
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/v4/jyh_4490_4_counter.v

@@ -20,42 +20,46 @@ begin
 		if(load)
 			begin
 			Q<=in;
-			end
-		else if(co_flag)
-		begin
-			co<=1;
-			co_flag=0;
-		end
-		else if(!co_flag)
 			co<=0;
-		//正反计数
-		 if(upd)
-			begin
-				if(Q>=4'd9)
-					begin
-					Q<=4'd0;
-					co_flag=1;
-					end
-				else
-					begin
-					Q <= Q+1;
-					end
 			end
 		else
+		begin
+			if(co_flag)
 			begin
-				if(Q<=4'd0)
+				co<=1;
-					begin
+				co_flag=0;
-					Q<=4'd9;
+			end
-					end
+			else if(!co_flag)
-				else if(Q==4'd1)
+				co<=0;
-					begin
+			//正反计数
-					Q <= Q-1;
+			 if(upd)
-					co_flag=1;
+				begin
-					end
+					if(Q>=4'd9)
-				else
+						begin
-					begin
+						Q<=4'd0;
-					Q <= Q-1;
+						co_flag=1;
-					end
+						end
+					else
+						begin
+						Q <= Q+1;
+						end
+				end
+			else 
+				begin
+					if(Q<=4'd0)
+						begin
+						Q<=4'd9;
+						end
+					else if(Q==4'd1)
+						begin
+						Q <= Q-1;
+						co_flag=1;
+						end
+					else
+						begin
+						Q <= Q-1;
+						end
+				end
 			end
 	end
 	else

Quartus/v4/jyh_4490_4_divider.v

@@ -1,8 +1,9 @@
 module jyh_4490_4_divider(clk,clk_out);
 	 input clk;
 	 output reg clk_out;
-    localparam TARGET=2;
+//    localparam TARGET=100000;
-    reg [15:0]counter=0; 
+	localparam TARGET=1;
+    reg [19:0]counter=0; 
     initial begin
         clk_out=0;
     end

Quartus/v4/jyh_4490_4_entry.v

@@ -1,21 +1,21 @@
-module jyh_4490_4_entry(out1,		out0,		code,			sel, 			CO,
+module jyh_4490_4_entry(out1,		out0,		code,			seg, 			CO,
 							//	十位输出 	个位输出 	数码管型码 	数码管位码 	进/借位标志位
-								in1,		in0,		load,		clk,			subclk, 		clr,			en,			upd);
+								in1,		in0,		load,		clk,			clk_50m,		subclk, 		clr,			en,			upd);
-							// 十位装载 	个位装载 	装载信号 	计数时钟信号  分频信号		清零信号 		使能信号 		正反计数标志位
+							// 十位装载 	个位装载 	装载信号 	计数时钟信号  50M			分频信号		清零信号 		使能信号 		正反计数标志位
 
 output [3:0] out1;
 output [3:0] out0;
 output [6:0] code;
-output [7:0] sel;
+output [7:0] seg;
 output CO;
 input [3:0] in1;
 input [3:0] in0;
-input clk,load,clr,en,upd;
+input clk,load,clr,en,upd,clk_50m;
 
 //分频器
 output subclk;
 jyh_4490_4_divider D1(
-.clk(clk),
+.clk(clk_50m),
 .clk_out(subclk)
 );
 
@@ -23,7 +23,7 @@ jyh_4490_4_divider D1(
 //个位计数器
 jyh_4490_4_counter C1(
 .Q(out0),
-.clk(subclk),
+.clk(clk),
 .co(CO),
 .clr(clr),
 .load(load),
@@ -34,8 +34,9 @@ jyh_4490_4_counter C1(
 //十位计数器
 jyh_4490_4_counter C2(
 .Q(out1),
-.clk(CO||load),
+.clk(CO||(load && clk)),
 .clr(clr),
+.in(in1),
 .load(load),
 .en(en),
 .upd(upd));
@@ -45,7 +46,7 @@ jyh_4490_4_encoder E1(
 .codeout(code),
 .d1(out0),
 .d2(out1),
-.clk(clk),
+.clk(subclk),
-.sel(sel[3:0])
+.sel(seg[3:0])
 );
 endmodule