18 lines
No EOL
337 B
Verilog
18 lines
No EOL
337 B
Verilog
module v2_entry_4490(clk_in,enable_in,Qout,seg_out,code_out);
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input clk_in,enable_in;
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output wire [2:0] Qout;
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output wire seg_out;
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output wire [6:0]code_out;
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//调用计数器模块
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jyh_4490_2_1 counter(
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.clk(clk_in),
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.en(enable_in),
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.Q(Qout));
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//调用译码器模块
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jyh_4490_2_2 encoder(
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.in(Qout),
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.out(code_out));
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endmodule |