33 lines
2.5 KiB
Text
33 lines
2.5 KiB
Text
# Compile of jyh_4490_6_entry.v was successful.
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vsim work.jyh_4490_6_testbench_top
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# vsim work.jyh_4490_6_testbench_top
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# Start time: 17:50:53 on May 10,2022
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# Loading work.jyh_4490_6_testbench_top
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# Loading work.jyh_4490_6_entry
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# Loading work.jyh_4490_6_divider
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# Loading work.jyh_4490_6_counter
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# Loading work.jyh_4490_4_encoder
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# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'C1'. Expected 7, found 4.
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/C1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 28
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'load'.
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'in'.
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'co'.
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# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'E1'. Expected 7, found 4.
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 35
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# ** Warning: (vsim-3015) [PCDPC] - Port size (7) does not match connection size (4) for port 'd1'. The port definition is at: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v(2).
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 35
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd2'.
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd3'.
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd4'.
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add wave -position end sim:/jyh_4490_6_testbench_top/clk
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add wave -position end sim:/jyh_4490_6_testbench_top/code
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add wave -position end sim:/jyh_4490_6_testbench_top/seg
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add wave -position end sim:/jyh_4490_6_testbench_top/cnt
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add wave -position end sim:/jyh_4490_6_testbench_top/in
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add wave -position end sim:/jyh_4490_6_testbench_top/en
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add wave -position end sim:/jyh_4490_6_testbench_top/subclk
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add wave -position end sim:/jyh_4490_6_testbench_top/out0
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run -all
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# Break key hit
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# Closing project /home/ir/Documents/codelib/Quartus/v6_testbench_top/jyh_4490_top.mpf
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# Simulation stop requested.
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