27 lines
No EOL
540 B
Verilog
27 lines
No EOL
540 B
Verilog
//七段一位译码器
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module jyh_4490_4_simpleEncoder(sel,codeout,clk, d1);
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input clk;
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input [6:0] d1;
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output reg sel; //位选
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output reg [6:0] codeout; //型码
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always @(clk)
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begin
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case (d1)
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4'd0: codeout<=7'b1111110;
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4'd1: codeout<=7'b0110000;
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4'd2: codeout<=7'b1101101;
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4'd3: codeout<=7'b1111001;
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4'd4: codeout<=7'b0110011;
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4'd5: codeout<=7'b1011011;
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4'd6: codeout<=7'b1011111;
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4'd7: codeout<=7'b1110000;
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4'd8: codeout<=7'b1111111;
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4'd9: codeout<=7'b1111011;
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default: codeout<=7'bx;
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endcase
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end
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endmodule |