92 lines
3.8 KiB
Text
92 lines
3.8 KiB
Text
# Compile of jyh_4490_6_testbench.v was successful.
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# Compile of jyh_4490_mstate.v was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.jyh_4490_6_testbench
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# vsim work.jyh_4490_6_testbench
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# Start time: 23:55:10 on May 09,2022
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# Loading work.jyh_4490_6_testbench
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# Loading work.jyh_4490_mstate
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# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'.
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39
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# Error loading design
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# End time: 23:55:10 on May 09,2022, Elapsed time: 0:00:00
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# Errors: 1, Warnings: 7
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vsim work.jyh_4490_6_testbench
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# vsim work.jyh_4490_6_testbench
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# Start time: 23:55:11 on May 09,2022
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# Loading work.jyh_4490_6_testbench
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# Loading work.jyh_4490_mstate
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# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'.
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39
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# Error loading design
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# End time: 23:55:11 on May 09,2022, Elapsed time: 0:00:00
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# Errors: 1, Warnings: 1
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# can't read "Startup(-L)": no such element in array
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# Load canceled
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# Compile of jyh_4490_6_testbench.v failed with 1 errors.
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# Compile of jyh_4490_6_testbench.v was successful.
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vsim work.jyh_4490_6_testbench
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# vsim work.jyh_4490_6_testbench
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# Start time: 23:57:01 on May 09,2022
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# Loading work.jyh_4490_6_testbench
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# Loading work.jyh_4490_mstate
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add wave -position end sim:/jyh_4490_6_testbench/clk
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add wave -position end sim:/jyh_4490_6_testbench/clr
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add wave -position end sim:/jyh_4490_6_testbench/in
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add wave -position end sim:/jyh_4490_6_testbench/out
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add wave -position end sim:/jyh_4490_6_testbench/cnt
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run -all
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# Compile of jyh_4490_6_testbench.v was successful.
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# Compile of jyh_4490_mstate.v was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.jyh_4490_6_testbench
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# End time: 23:59:24 on May 09,2022, Elapsed time: 0:02:23
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# Errors: 0, Warnings: 4
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# vsim work.jyh_4490_6_testbench
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# Start time: 23:59:24 on May 09,2022
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# Loading work.jyh_4490_6_testbench
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# Loading work.jyh_4490_mstate
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add wave -position end sim:/jyh_4490_6_testbench/clk
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add wave -position end sim:/jyh_4490_6_testbench/in
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add wave -position end sim:/jyh_4490_6_testbench/out
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add wave -position end sim:/jyh_4490_6_testbench/cnt
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run -all
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# Compile of jyh_4490_6_testbench.v was successful.
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# Compile of jyh_4490_mstate.v was successful.
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# 2 compiles, 0 failed with no errors.
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# running
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vsim work.jyh_4490_6_testbench
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# End time: 00:03:02 on May 10,2022, Elapsed time: 0:03:38
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# Errors: 0, Warnings: 2
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# vsim work.jyh_4490_6_testbench
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# Start time: 00:03:02 on May 10,2022
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# Loading work.jyh_4490_6_testbench
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# Loading work.jyh_4490_mstate
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# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4.
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# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 38
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# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(38): [TFMPC] - Missing connection for port 'en'.
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add wave -position end sim:/jyh_4490_6_testbench/clk
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add wave -position end sim:/jyh_4490_6_testbench/in
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add wave -position end sim:/jyh_4490_6_testbench/en
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add wave -position end sim:/jyh_4490_6_testbench/out
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add wave -position end sim:/jyh_4490_6_testbench/cnt
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run -all
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# Break key hit
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# Simulation stop requested.
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# End time: 00:05:02 on May 10,2022, Elapsed time: 0:02:00
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# Errors: 0, Warnings: 4
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