26 lines
No EOL
242 B
Verilog
26 lines
No EOL
242 B
Verilog
`timescale 1ns/1ns
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module tb;
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reg clk;
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reg key;
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wire [3:0] out;
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initial begin
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clk=0;
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key=0;
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end
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always#10 clk=~clk;
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always begin
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repeat(10)
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#15 key=~key;
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repeat(10)
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#15 key=0;
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end
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mstate M1(
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.clk(clk),
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.key(key),
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.out(out));
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endmodule |