This repository has been archived on 2024-01-06. You can view files and clone it, but cannot push or open issues or pull requests.
justhomework/Quartus/UART_Design/uart_screen/synthesis/submodules
2022-06-25 17:00:22 +08:00
..
altera_reset_controller.sdc feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_reset_controller.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_reset_synchronizer.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_rs232_counters.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_rs232_in_deserializer.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_rs232_out_serializer.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_sync_fifo.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
uart_screen_rs232_0.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00