feat(数电课设): 差不多
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iridiumR
parent
6116e09e28
commit
5455fc6d81
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@ -1,91 +0,0 @@
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module design(
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input wire clk,//50MHz时钟
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output reg led, //用于指示
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input wire rst_n,
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input wire rxd,
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output wire txd,
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inout dht_io
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);
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reg [31:0]cnt;
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reg led_f1,tx_flag;
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always@(posedge clk)
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begin
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led_f1 <= led;
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tx_flag <= led &(~led_f1);
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if(cnt >= 32'd25000000 - 1)
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begin
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cnt <= 0;
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led <=~led;
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end
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else begin
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cnt <= cnt + 1'b1 ;
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end
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end
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//--------------------------------------------
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localparam s_s1=0;
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localparam s_s2=1;
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localparam s_s3=2;
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localparam s_s4=3;
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reg [7:0]send_data;
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reg to_uart_valid , to_uart_ready;
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reg [2:0]send_st;
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reg [7:0]data_cnt;
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always@(posedge clk)
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begin
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if(!rst_n)begin
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to_uart_ready <= 1'b0;
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to_uart_valid <= 1'b0;
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send_data <= 8'd0;
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send_st<= s_s1;
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data_cnt <= 8'd0;
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end
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else begin
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case(send_st)
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s_s1:begin//待机
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if(tx_flag)begin
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send_st <= s_s2;
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to_uart_valid <= 1'b0;
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to_uart_ready<= 1'b0;
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data_cnt <= 8'd0;
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send_data <= 9;
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end
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else begin
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to_uart_valid <= 1'b0;
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to_uart_ready<= 1'b0;
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end
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end
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s_s2:begin
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if(data_cnt <= 8'd8-1'b1)begin
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to_uart_valid <= 1'b1;
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send_data <= data_cnt+1;
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data_cnt <= data_cnt + 1'b1;
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send_st <= (data_cnt >= 8'd5-1)?s_s3:s_s2;
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end
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end
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s_s3:begin
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to_uart_valid <= 1'b0;
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to_uart_ready <= 1'b1;
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send_st <= s_s1;
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data_cnt<=8'd0;
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end
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default :send_st <= s_s1;
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endcase
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end
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end
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uart_screen u0 (
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.rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data
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.rs232_0_to_uart_error (), // .error
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.rs232_0_to_uart_valid (to_uart_valid), // .valid
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.rs232_0_to_uart_ready (to_uart_ready), // .ready
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.rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD
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.rs232_0_UART_TXD (txd), // .TXD
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.clk_clk (clk), // clk.clk
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.reset_reset_n (rst_n) // reset.reset_n
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);
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endmodule
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@ -0,0 +1,107 @@
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module UART_design(
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input wire clk, //50MHz clock
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output reg led, //led
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input wire rst_n, //rst
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input wire rxd, // UART RXD
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output wire txd // UART TXD
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);
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reg [31:0]cnt; //Clock Posedge Counter
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reg led_f1,tx_flag; //Flags
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localparam s_s1=0; //State Machine Param
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localparam s_s2=1;
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localparam s_s3=2;
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localparam s_s4=3;
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reg [7:0]data[64]; //UART Data to be send
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reg [7:0]send_data; //UART Send Buffer
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//IP Core register
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reg to_uart_valid , to_uart_ready;
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reg [2:0]send_st;
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reg [7:0]data_cnt;
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//Save Data
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initial begin
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data[0]=8'h67; data[1]=8'h30; data[2]=8'h2E; data[3]=8'h74; data[4]=8'h78; data[5]=8'h74; data[6]=8'h3D; data[7]=8'h22;
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data[8]=8'hCF; data[9]=8'hB2; data[10]=8'hD3;data[11]=8'hAD; data[12]=8'hB6;data[13]=8'hFE;data[14]=8'hCA;data[15]=8'hAE;
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data[16]=8'hB4;data[17]=8'hF3;data[18]=8'hA1;data[19]=8'hA2; data[20]=8'hD3;data[21]=8'hC0;data[22]=8'hD4;data[23]=8'hB6;
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data[24]=8'hB8;data[25]=8'hFA;data[26]=8'hB5;data[27]=8'hB3; data[28]=8'hD7;data[29]=8'hDF;data[29]=8'hA1;data[31]=8'hA2;
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data[32]=8'hB7;data[33]=8'hDC;data[34]=8'hBD;data[35]=8'hF8; data[36]=8'hD0;data[37]=8'hC2;data[38]=8'hD5;data[39]=8'hF7;
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data[40]=8'hB3;data[41]=8'hCC;data[42]=8'hA1;data[43]=8'hA3; data[44]=8'h22;data[45]=8'hFF;data[46]=8'hFF;data[47]=8'hFF;
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data[48]=8'h70;data[49]=8'h30;data[50]=8'h2E;data[51]=8'h70; data[52]=8'h69;data[53]=8'h63;data[54]=8'h3D;data[55]=8'h30;
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data[56]=8'hFF;data[57]=8'hFF;data[58]=8'hFF;data[59]=8'h00; data[60]=8'h00;data[61]=8'h00;data[62]=8'h00;data[63]=8'h00;
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end
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always@(posedge clk)
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begin
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led_f1 <= led;
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tx_flag <= led &(~led_f1);
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if(cnt >= 32'd25000000 - 1)
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begin
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cnt <= 0;
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led <=~led;
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end
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else begin
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cnt <= cnt + 1'b1 ;
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end
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end
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always@(posedge clk)
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begin
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if(!rst_n)begin
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to_uart_ready <= 1'b0;
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to_uart_valid <= 1'b0;
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send_data <= 8'd0;
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send_st<= s_s1;
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data_cnt <= 8'd0;
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end
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else begin
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case(send_st)
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s_s1:begin //s1:idle
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if(tx_flag)begin
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send_st <= s_s2;
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to_uart_valid <= 1'b0;
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to_uart_ready<= 1'b0;
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data_cnt <= 8'd0;
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send_data <= 9;
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end
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else begin
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to_uart_valid <= 1'b0;
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to_uart_ready<= 1'b0;
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end
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end
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s_s2:begin //s2:send
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if(data_cnt <= 8'd64-1'b1)begin
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to_uart_valid <= 1'b1;
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send_data <= data[data_cnt];
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data_cnt <= data_cnt + 1'b1;
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send_st <= (data_cnt >= 8'd64-1'b1)?s_s3:s_s2;
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end
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end
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s_s3:begin //s2:send over
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to_uart_valid <= 1'b0;
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to_uart_ready <= 1'b1;
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send_st <= s_s1;
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data_cnt<=8'd0;
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end
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default :send_st <= s_s1;
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endcase
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end
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end
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uart_screen u0 (
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.rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data
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.rs232_0_to_uart_error (), // .error
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.rs232_0_to_uart_valid (to_uart_valid), // .valid
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.rs232_0_to_uart_ready (to_uart_ready), // .ready
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.rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD
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.rs232_0_UART_TXD (txd), // .TXD
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.clk_clk (clk), // clk.clk
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.reset_reset_n (rst_n) // reset.reset_n
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);
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endmodule
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@ -39,7 +39,7 @@
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE6E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY design
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set_global_assignment -name TOP_LEVEL_ENTITY UART_design
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:36:33 五月 24, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
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@ -48,7 +48,11 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name QSYS_FILE uart_screen.qsys
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name VERILOG_FILE design.v
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set_global_assignment -name VERILOG_FILE UART_design.v
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set_global_assignment -name QSYS_FILE uart_screen.qsys
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="uart_screen" kind="uart_screen" version="1.0" fabric="QSYS">
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<!-- Format version 21.1 842 (Future versions may contain additional information.) -->
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<!-- 2022.06.14.11:25:23 -->
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<!-- 2022.06.25.16:59:31 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1655177123</value>
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<value>1656147571</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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