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justhomework/Quartus/UART_Design/UART/synthesis/submodules
2022-06-25 17:00:22 +08:00
..
altera_up_rs232_counters.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_rs232_in_deserializer.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_rs232_out_serializer.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
altera_up_sync_fifo.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00
UART_rs232_0.v feat(数电课设): 差不多 2022-06-25 17:00:22 +08:00